summaryrefslogtreecommitdiffstats
path: root/drivers/ssb
diff options
context:
space:
mode:
authorHauke Mehrtens <hauke@hauke-m.de>2012-11-27 00:31:55 +0100
committerJohn W. Linville <linville@tuxdriver.com>2012-11-30 13:38:14 -0500
commit0362063b7be97f6f8e2c644b970f5726489aacdf (patch)
tree11230e5afa3c4c74499a5dfa895a419a22b57ea4 /drivers/ssb
parent4a7267c9a03b9627e5e85c80b307eb4541bab902 (diff)
downloadlinux-0362063b7be97f6f8e2c644b970f5726489aacdf.tar.gz
linux-0362063b7be97f6f8e2c644b970f5726489aacdf.tar.bz2
linux-0362063b7be97f6f8e2c644b970f5726489aacdf.zip
ssb: extif: fix compile errors
If CONFIG_SSB_EMBEDDED or CONFIG_SSB_DRIVER_MIPS is set and CONFIG_SSB_DRIVER_EXTIF is not set, it will cause compile problems because of missing functions. This patch fixes these problems. The mips driver now also uses ssb_chipco_available() instead of checking bus->chipco.dev manually. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/ssb')
-rw-r--r--drivers/ssb/driver_mipscore.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c
index b918ba922306..5bd05b136d22 100644
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
{
struct ssb_bus *bus = mcore->dev->bus;
- if (bus->extif.dev)
+ if (ssb_extif_available(&bus->extif))
mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
- else if (bus->chipco.dev)
+ else if (ssb_chipco_available(&bus->chipco))
mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
else
mcore->nr_serial_ports = 0;
@@ -191,7 +191,7 @@ static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
struct ssb_bus *bus = mcore->dev->bus;
/* When there is no chipcommon on the bus there is 4MB flash */
- if (!bus->chipco.dev) {
+ if (!ssb_chipco_available(&bus->chipco)) {
mcore->pflash.present = true;
mcore->pflash.buswidth = 2;
mcore->pflash.window = SSB_FLASH1;
@@ -227,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
return ssb_pmu_get_cpu_clock(&bus->chipco);
- if (bus->extif.dev) {
+ if (ssb_extif_available(&bus->extif)) {
ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
- } else if (bus->chipco.dev) {
+ } else if (ssb_chipco_available(&bus->chipco)) {
ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
} else
return 0;
@@ -265,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore)
hz = 100000000;
ns = 1000000000 / hz;
- if (bus->extif.dev)
+ if (ssb_extif_available(&bus->extif))
ssb_extif_timing_init(&bus->extif, ns);
- else if (bus->chipco.dev)
+ else if (ssb_chipco_available(&bus->chipco))
ssb_chipco_timing_init(&bus->chipco, ns);
/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */