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author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2019-04-17 13:58:37 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-04-19 15:01:34 +0200 |
commit | 9445ccb3714c78c26a3a25fafed4d9d965080431 (patch) | |
tree | 0a76cbd8a06e540c3be6910c8391d70f0f4dc125 /drivers/staging/mt7621-pci-phy | |
parent | d43f53c6cc926b18316a7e835348363e4a10b61e (diff) | |
download | linux-9445ccb3714c78c26a3a25fafed4d9d965080431.tar.gz linux-9445ccb3714c78c26a3a25fafed4d9d965080431.tar.bz2 linux-9445ccb3714c78c26a3a25fafed4d9d965080431.zip |
staging: mt7621-pci-phy: add quirks for 'E2' revision using 'soc_device_attribute'
Depending on revision of the chip, 'mt7621_bypass_pipe_rst' function
must be executed. Add better support for this using 'soc_device_match'
in driver probe function.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci-phy')
-rw-r--r-- | drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c index 21f980cc2d8f..f762369d6792 100644 --- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c +++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c @@ -11,11 +11,11 @@ #include <linux/of_device.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> +#include <linux/sys_soc.h> #include <mt7621.h> #include <ralink_regs.h> #define RALINK_CLKCFG1 0x30 -#define CHIP_REV_MT7621_E2 0x0101 #define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) @@ -97,11 +97,14 @@ struct mt7621_pci_phy_instance { * @dev: pointer to device * @phys: pointer to Mt7621 PHY device * @nphys: number of PHY devices for this core + * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst' + * needs to be executed. Depends on chip revision. */ struct mt7621_pci_phy { struct device *dev; struct mt7621_pci_phy_instance **phys; int nphys; + bool bypass_pipe_rst; }; static inline u32 phy_read(struct mt7621_pci_phy_instance *instance, u32 reg) @@ -232,9 +235,8 @@ static int mt7621_pci_phy_init(struct phy *phy) { struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy); struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent); - u32 chip_rev_id = rt_sysc_r32(SYSC_REG_CHIP_REV); - if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2) + if (mphy->bypass_pipe_rst) mt7621_bypass_pipe_rst(mphy, instance); mt7621_set_phy_for_ssc(mphy, instance); @@ -305,9 +307,14 @@ static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev, return mt7621_phy->phys[args->args[0]]->phy; } +static const struct soc_device_attribute mt7621_pci_quirks_match[] = { + { .soc_id = "mt7621", .revision = "E2" } +}; + static int mt7621_pci_phy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + const struct soc_device_attribute *attr; struct phy_provider *provider; struct mt7621_pci_phy *phy; struct resource *res; @@ -324,6 +331,10 @@ static int mt7621_pci_phy_probe(struct platform_device *pdev) if (!phy->phys) return -ENOMEM; + attr = soc_device_match(mt7621_pci_quirks_match); + if (attr) + phy->bypass_pipe_rst = true; + phy->dev = dev; platform_set_drvdata(pdev, phy); |