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| author | Sahil Siddiq <sahilcdq0@gmail.com> | 2025-04-19 21:18:19 +0530 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2025-04-20 07:06:54 +0100 |
| commit | 4e6d24a309e60251439f08f15de37b489465f17b (patch) | |
| tree | 49cdf603d32fcf154001278ce7c72ed52f364c71 /drivers/usb/cdns3/cdns3-debug.h | |
| parent | 0c4a6e79ef522554bc509294dfe69b24ee78205d (diff) | |
| download | linux-4e6d24a309e60251439f08f15de37b489465f17b.tar.gz linux-4e6d24a309e60251439f08f15de37b489465f17b.tar.bz2 linux-4e6d24a309e60251439f08f15de37b489465f17b.zip | |
openrisc: Add cacheinfo support
Add cacheinfo support for OpenRISC.
Currently, a few CPU cache attributes pertaining to OpenRISC processors
are exposed along with other unrelated CPU attributes in the procfs file
system (/proc/cpuinfo). However, a few cache attributes remain unexposed.
Provide a mechanism that the generic cacheinfo infrastructure can employ
to expose these attributes via the sysfs file system. These attributes
can then be exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Move
the implementation to pull cache attributes from the processor's
registers from arch/openrisc/kernel/setup.c with a few modifications.
This implementation is based on similar work done for MIPS and LoongArch.
Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Sahil Siddiq <sahilcdq0@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'drivers/usb/cdns3/cdns3-debug.h')
0 files changed, 0 insertions, 0 deletions