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| author | Guoqing Zhang <guoqing.zhang@intel.com> | 2017-04-07 17:56:54 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-04-08 12:17:40 +0200 |
| commit | 0f1d832ed1fb9527a4cc5fcb8511e85fd0a85185 (patch) | |
| tree | 5c597054f52b31cb69971d0bd4393a03d25be646 /drivers/usb/host/xhci.h | |
| parent | 26bba5c767de6724f330cdc2ad28bb783674f5a0 (diff) | |
| download | linux-0f1d832ed1fb9527a4cc5fcb8511e85fd0a85185.tar.gz linux-0f1d832ed1fb9527a4cc5fcb8511e85fd0a85185.tar.bz2 linux-0f1d832ed1fb9527a4cc5fcb8511e85fd0a85185.zip | |
usb: xhci: Add port test modes support for usb2.
For usb2 ports, the port test mode Test_J_State, Test_K_State,
Test_Packet, Test_SE0_NAK and Test_Force_En can be enabled
as described in usb2 spec.
USB2 test mode is a required hardware feature for system integrators
validating their hardware according to USB spec, regarding signal
strength and stuff. It is purely a hardware test feature.
Usually you need an oscilloscope and have to enable those test modes on
the hardware. This will send some specific test patterns on D+/D-. There
is no report available (in Linux itself) as it is purely externally
visible. Regular USB usage is not possible at that time.
Anyone (well access to e.g. /dev/bus/usb/001/001 provided) can use it by
sending appropriate USB_PORT_FEAT_TEST requests to the hub.
[Add better commit message by Alexander Stein -Mathias]
Signed-off-by: Guoqing Zhang <guoqing.zhang@intel.com>
Cc: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/host/xhci.h')
| -rw-r--r-- | drivers/usb/host/xhci.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 4e12c8cb557a..675d552e420e 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -425,6 +425,7 @@ struct xhci_op_regs { #define PORT_L1DS_MASK (0xff << 8) #define PORT_L1DS(p) (((p) & 0xff) << 8) #define PORT_HLE (1 << 16) +#define PORT_TEST_MODE_SHIFT 28 /* USB3 Protocol PORTLI Port Link Information */ #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) @@ -1843,6 +1844,7 @@ struct xhci_hcd { /* Compliance Mode Recovery Data */ struct timer_list comp_mode_recovery_timer; u32 port_status_u0; + u16 test_mode; /* Compliance Mode Timer Triggered every 2 seconds */ #define COMP_MODE_RCVRY_MSECS 2000 |