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| author | Richard Cochran <richardcochran@gmail.com> | 2020-05-24 11:27:10 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-05-25 17:55:17 -0700 |
| commit | eabd5c9dd0c0b8d471d144801c8302a4eff6eb27 (patch) | |
| tree | 9f3a0283aed87fe5cd117a49e7dc9eeb5439e3db /drivers | |
| parent | 45af29ca761c275e350cca659856bc56f1035ef9 (diff) | |
| download | linux-eabd5c9dd0c0b8d471d144801c8302a4eff6eb27.tar.gz linux-eabd5c9dd0c0b8d471d144801c8302a4eff6eb27.tar.bz2 linux-eabd5c9dd0c0b8d471d144801c8302a4eff6eb27.zip | |
ptp_clock: Let the ADJ_OFFSET interface respect the ADJ_NANO flag for PHC devices.
In commit 184ecc9eb260d5a3bcdddc5bebd18f285ac004e9 ("ptp: Add adjphase
function to support phase offset control.") the PTP Hardware Clock
interface expanded to support the ADJ_OFFSET offset mode. However,
the implementation did not respect the traditional yet pedantic
distinction between units of microseconds and nanoseconds signaled by
the ADJ_NANO flag. This patch fixes the issue by adding logic to
handle that flag.
Signed-off-by: Richard Cochran <richardcochran@gmail.com>
Reviewed-by: Vincent Cheng <vincent.cheng.xh@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ptp/ptp_clock.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c index fc984a8828fb..03a246e60fd9 100644 --- a/drivers/ptp/ptp_clock.c +++ b/drivers/ptp/ptp_clock.c @@ -147,8 +147,14 @@ static int ptp_clock_adjtime(struct posix_clock *pc, struct __kernel_timex *tx) err = ops->adjfreq(ops, ppb); ptp->dialed_frequency = tx->freq; } else if (tx->modes & ADJ_OFFSET) { - if (ops->adjphase) - err = ops->adjphase(ops, tx->offset); + if (ops->adjphase) { + s32 offset = tx->offset; + + if (!(tx->modes & ADJ_NANO)) + offset *= NSEC_PER_USEC; + + err = ops->adjphase(ops, offset); + } } else if (tx->modes == 0) { tx->freq = ptp->dialed_frequency; err = 0; |