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| author | Tero Kristo <t-kristo@ti.com> | 2020-04-29 16:13:41 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-05-14 12:54:46 -0700 |
| commit | f968045fb92e5408c25f1b4eae21bab4882e88e8 (patch) | |
| tree | 708cb6cbaf1c11e37f19eee01ab89cf6ea5f5f7e /drivers | |
| parent | 74c0ac108d42bf24d37aaea68b6d39ba52d5f0e2 (diff) | |
| download | linux-f968045fb92e5408c25f1b4eae21bab4882e88e8.tar.gz linux-f968045fb92e5408c25f1b4eae21bab4882e88e8.tar.bz2 linux-f968045fb92e5408c25f1b4eae21bab4882e88e8.zip | |
clk: ti: omap5: Add proper parent clocks for l4-secure clocks
L4 secure clocks do not have their parents set currently, which ends
them up to the orphan clock list. Fix this by adding either l3 or l4
clock as their parent.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Link: https://lkml.kernel.org/r/20200429131341.4697-4-t-kristo@ti.com
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/ti/clk-54xx.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 92bf2dda95b9..8694bc9f5fc7 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -303,13 +303,13 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst static const struct omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = { - { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "" }, - { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "" }, - { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "" }, - { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "" }, - { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, - { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "" }, - { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, + { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, + { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" }, + { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" }, { 0 }, }; |