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authorDario Binacchi <dario.binacchi@amarulasolutions.com>2023-11-11 11:41:50 +0100
committerHelge Deller <deller@gmx.de>2024-01-11 17:09:00 +0100
commit5758844105f7dd9a0a04990cd92499a1a593dd36 (patch)
tree00fe7533f4779914d5f997453b33d24f13ba69cc /fs
parentde927f6c0b07d9e698416c5b287c521b07694cac (diff)
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fbdev: imxfb: fix left margin setting
The previous setting did not take into account the CSTN mode. For the H_WAIT_2 bitfield (bits 0-7) of the LCDC Horizontal Configuration Register (LCDCR), the IMX25RM manual states that: In TFT mode, it specifies the number of SCLK periods between the end of HSYNC and the beginning of OE signal, and the total delay time equals (H_WAIT_2 + 3) of SCLK periods. In CSTN mode, it specifies the number of SCLK periods between the end of HSYNC and the first display data in each line, and the total delay time equals (H_WAIT_2 + 2) of SCLK periods. The patch handles both cases. Fixes: 4e47382fbca9 ("fbdev: imxfb: warn about invalid left/right margin") Fixes: 7e8549bcee00 ("imxfb: Fix margin settings") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Helge Deller <deller@gmx.de>
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