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| author | Michael Hennerich <michael.hennerich@analog.com> | 2007-10-30 11:53:55 +0800 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-10-30 11:53:55 +0800 |
| commit | be0f3131a9cc7239d438b5016643e3eb9c8d8c21 (patch) | |
| tree | 92763b89a534e99bcf4a29838333c3ce52cd21a9 /include/asm-blackfin/mach-bf527 | |
| parent | 111cf97d2cf35fbaa5eaff6ec5d395a06e14aadf (diff) | |
| download | linux-be0f3131a9cc7239d438b5016643e3eb9c8d8c21.tar.gz linux-be0f3131a9cc7239d438b5016643e3eb9c8d8c21.tar.bz2 linux-be0f3131a9cc7239d438b5016643e3eb9c8d8c21.zip | |
Blackfin arch: Do not pollute name space used in linux-2.6.x/sound
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf527')
| -rw-r--r-- | include/asm-blackfin/mach-bf527/defBF52x_base.h | 86 |
1 files changed, 43 insertions, 43 deletions
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h index d6c24c54699d..fc69cf93f149 100644 --- a/include/asm-blackfin/mach-bf527/defBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h @@ -1718,55 +1718,55 @@ /* Bit masks for HOST_CONTROL */ -#define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 -#define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 -#define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 -#define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 -#define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 -#define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 -#define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 -#define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 -#define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 -#define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 +#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ +#define HOST_CNTR_nHOST_EN 0x0 +#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ +#define HOST_CNTR_nHOST_END 0x0 +#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ +#define HOST_CNTR_nDATA_SIZE 0x0 +#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ +#define HOST_CNTR_nHOST_RST 0x0 +#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ +#define HOST_CNTR_nHRDY_OVR 0x0 +#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ +#define HOST_CNTR_nINT_MODE 0x0 +#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ +#define HOST_CNTR_ nBT_EN 0x0 +#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ +#define HOST_CNTR_nEHW 0x0 +#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ +#define HOST_CNTR_nEHR 0x0 +#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ +#define HOST_CNTR_nBDR 0x0 /* Bit masks for HOST_STATUS */ -#define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 -#define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 -#define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 -#define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 -#define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 -#define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 -#define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 -#define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 -#define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 -#define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 -#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ -#define nHOSTRD_DONE 0x0 +#define HOST_STAT_READY 0x1 /* DMA Ready */ +#define HOST_STAT_nREADY 0x0 +#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ +#define HOST_STAT_nFIFOFULL 0x0 +#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ +#define HOST_STAT_nFIFOEMPTY 0x0 +#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ +#define HOST_STAT_nCOMPLETE 0x0 +#define HOST_STAT_HSHK 0x10 /* Host Handshake */ +#define HOST_STAT_nHSHK 0x0 +#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ +#define HOST_STAT_nTIMEOUT 0x0 +#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ +#define HOST_STAT_nHIRQ 0x0 +#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define HOST_STAT_nALLOW_CNFG 0x0 +#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ +#define HOST_STAT_nDMA_DIR 0x0 +#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ +#define HOST_STAT_nBTE 0x0 +#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ +#define HOST_STAT_nHOSTRD_DONE 0x0 /* Bit masks for HOST_TIMEOUT */ -#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ +#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ /* Bit masks for CNT_CONFIG */ |