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| author | Emil Renner Berthing <kernel@esmil.dk> | 2023-04-01 19:19:14 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-04-05 15:43:24 +0100 |
| commit | 3de0c91032580d4923624fe6ee773eddd1b574bc (patch) | |
| tree | b4db106fba33abc864b26e0200690c8105e63d76 /include/dt-bindings/reset | |
| parent | 7fce1e39f01900a294cd2c456c77f3e2512e0634 (diff) | |
| download | linux-3de0c91032580d4923624fe6ee773eddd1b574bc.tar.gz linux-3de0c91032580d4923624fe6ee773eddd1b574bc.tar.bz2 linux-3de0c91032580d4923624fe6ee773eddd1b574bc.zip | |
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
Add bindings for the always-on clock and reset generator (AONCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'include/dt-bindings/reset')
| -rw-r--r-- | include/dt-bindings/reset/starfive,jh7110-crg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index b88216a4fe40..d78e38690ceb 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -139,4 +139,16 @@ #define JH7110_SYSRST_END 126 +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ |