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authorLinus Torvalds <torvalds@linux-foundation.org>2021-02-22 10:31:29 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2021-02-22 10:31:29 -0800
commitd652ea30ba32db12fe8365182fad5ba2e7c22822 (patch)
treebf2352dd0e4f9c232ead71b0087a2324029074cd /include/dt-bindings
parent3672ac8ac0d8bece188f82c48770bbe40f234f1e (diff)
parent45e606f2726926b04094e1c9bf809bca4884c57f (diff)
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Merge tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel: - ARM SMMU and Mediatek updates from Will Deacon: - Support for MT8192 IOMMU from Mediatek - Arm v7s io-pgtable extensions for MT8192 - Removal of TLBI_ON_MAP quirk - New Qualcomm compatible strings - Allow SVA without hardware broadcast TLB maintenance on SMMUv3 - Virtualization Host Extension support for SMMUv3 (SVA) - Allow SMMUv3 PMU perf driver to be built independently from IOMMU - Some tidy-up in IOVA and core code - Conversion of the AMD IOMMU code to use the generic IO-page-table framework - Intel VT-d updates from Lu Baolu: - Audit capability consistency among different IOMMUs - Add SATC reporting structure support - Add iotlb_sync_map callback support - SDHI support for Renesas IOMMU driver - Misc cleanups and other small improvments * tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (94 commits) iommu/amd: Fix performance counter initialization MAINTAINERS: repair file pattern in MEDIATEK IOMMU DRIVER iommu/mediatek: Fix error code in probe() iommu/mediatek: Fix unsigned domid comparison with less than zero iommu/vt-d: Parse SATC reporting structure iommu/vt-d: Add new enum value and structure for SATC iommu/vt-d: Add iotlb_sync_map callback iommu/vt-d: Move capability check code to cap_audit files iommu/vt-d: Audit IOMMU Capabilities and add helper functions iommu/vt-d: Fix 'physical' typos iommu: Properly pass gfp_t in _iommu_map() to avoid atomic sleeping iommu/vt-d: Fix compile error [-Werror=implicit-function-declaration] driver/perf: Remove ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3 MAINTAINERS: Add entry for MediaTek IOMMU iommu/mediatek: Add mt8192 support iommu/mediatek: Remove unnecessary check in attach_device iommu/mediatek: Support master use iova over 32bit iommu/mediatek: Add iova reserved function iommu/mediatek: Support for multi domains iommu/mediatek: Add get_domain_id from dev->dma_range_map ...
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/memory/mt2701-larb-port.h4
-rw-r--r--include/dt-bindings/memory/mt2712-larb-port.h6
-rw-r--r--include/dt-bindings/memory/mt6779-larb-port.h6
-rw-r--r--include/dt-bindings/memory/mt8167-larb-port.h6
-rw-r--r--include/dt-bindings/memory/mt8173-larb-port.h6
-rw-r--r--include/dt-bindings/memory/mt8183-larb-port.h6
-rw-r--r--include/dt-bindings/memory/mt8192-larb-port.h243
-rw-r--r--include/dt-bindings/memory/mtk-memory-port.h15
8 files changed, 275 insertions, 17 deletions
diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h
index 2d85c2ec6cfd..25d03526f142 100644
--- a/include/dt-bindings/memory/mt2701-larb-port.h
+++ b/include/dt-bindings/memory/mt2701-larb-port.h
@@ -4,8 +4,8 @@
* Author: Honghui Zhang <honghui.zhang@mediatek.com>
*/
-#ifndef _MT2701_LARB_PORT_H_
-#define _MT2701_LARB_PORT_H_
+#ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
/*
* Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h
index 6f9aa7349cef..e41a2841bcff 100644
--- a/include/dt-bindings/memory/mt2712-larb-port.h
+++ b/include/dt-bindings/memory/mt2712-larb-port.h
@@ -3,10 +3,10 @@
* Copyright (c) 2017 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
*/
-#ifndef __DTS_IOMMU_PORT_MT2712_H
-#define __DTS_IOMMU_PORT_MT2712_H
+#ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-memory-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h
index 2ad0899fbf2f..3fb438a96e35 100644
--- a/include/dt-bindings/memory/mt6779-larb-port.h
+++ b/include/dt-bindings/memory/mt6779-larb-port.h
@@ -4,10 +4,10 @@
* Author: Chao Hao <chao.hao@mediatek.com>
*/
-#ifndef _DTS_IOMMU_PORT_MT6779_H_
-#define _DTS_IOMMU_PORT_MT6779_H_
+#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-memory-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h
index 000fb299a408..aae57d4824ca 100644
--- a/include/dt-bindings/memory/mt8167-larb-port.h
+++ b/include/dt-bindings/memory/mt8167-larb-port.h
@@ -5,10 +5,10 @@
* Author: Honghui Zhang <honghui.zhang@mediatek.com>
* Author: Fabien Parent <fparent@baylibre.com>
*/
-#ifndef __DTS_IOMMU_PORT_MT8167_H
-#define __DTS_IOMMU_PORT_MT8167_H
+#ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-memory-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h
index 9f31ccfeca21..167a7fc51868 100644
--- a/include/dt-bindings/memory/mt8173-larb-port.h
+++ b/include/dt-bindings/memory/mt8173-larb-port.h
@@ -3,10 +3,10 @@
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
*/
-#ifndef __DTS_IOMMU_PORT_MT8173_H
-#define __DTS_IOMMU_PORT_MT8173_H
+#ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-memory-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h
index 2c579f305162..36abdf0ce5a2 100644
--- a/include/dt-bindings/memory/mt8183-larb-port.h
+++ b/include/dt-bindings/memory/mt8183-larb-port.h
@@ -3,10 +3,10 @@
* Copyright (c) 2018 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
*/
-#ifndef __DTS_IOMMU_PORT_MT8183_H
-#define __DTS_IOMMU_PORT_MT8183_H
+#ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_
-#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#include <dt-bindings/memory/mtk-memory-port.h>
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
diff --git a/include/dt-bindings/memory/mt8192-larb-port.h b/include/dt-bindings/memory/mt8192-larb-port.h
new file mode 100644
index 000000000000..23035a52c675
--- /dev/null
+++ b/include/dt-bindings/memory/mt8192-larb-port.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ *
+ * Author: Chao Hao <chao.hao@mediatek.com>
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_
+
+#include <dt-bindings/memory/mtk-memory-port.h>
+
+/*
+ * MM IOMMU supports 16GB dma address.
+ *
+ * The address will preassign like this:
+ *
+ * modules dma-address-region larbs-ports
+ * disp 0 ~ 4G larb0/1
+ * vcodec 4G ~ 8G larb4/5/7
+ * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
+ * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
+ * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5
+ *
+ * larb3/6/8/10/12/15 is null.
+ */
+
+/* larb0 */
+#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0)
+#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_ID(0, 1)
+#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2)
+#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 3)
+#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 4)
+#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5)
+
+/* larb1 */
+#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_ID(1, 0)
+#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_ID(1, 1)
+#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 2)
+#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 3)
+#define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_ID(1, 4)
+#define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_ID(1, 5)
+#define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_ID(1, 6)
+#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7)
+
+/* larb2 */
+#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0)
+#define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1)
+#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2)
+#define M4U_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3)
+#define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_ID(2, 4)
+
+/* larb3: null */
+
+/* larb4 */
+#define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_ID(4, 0)
+#define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_ID(4, 1)
+#define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_ID(4, 2)
+#define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3)
+#define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4)
+#define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5)
+#define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_ID(4, 6)
+#define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
+#define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_ID(4, 8)
+#define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9)
+#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 10)
+
+/* larb5 */
+#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_ID(5, 0)
+#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(5, 1)
+#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(5, 2)
+#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(5, 3)
+#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_ID(5, 4)
+#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(5, 5)
+#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_ID(5, 6)
+#define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7)
+
+/* larb6: null */
+
+/* larb7 */
+#define M4U_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0)
+#define M4U_PORT_L7_VENC_REC MTK_M4U_ID(7, 1)
+#define M4U_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2)
+#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3)
+#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4)
+#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5)
+#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6)
+#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7)
+#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8)
+#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9)
+#define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_ID(7, 10)
+#define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_ID(7, 11)
+#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12)
+#define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_ID(7, 13)
+#define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_ID(7, 14)
+
+/* larb8: null */
+
+/* larb9 */
+#define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0)
+#define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1)
+#define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2)
+#define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3)
+#define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_ID(9, 4)
+#define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5)
+#define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6)
+#define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7)
+#define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8)
+#define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9)
+#define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10)
+#define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11)
+#define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12)
+#define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13)
+#define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14)
+
+/* larb10: null */
+
+/* larb11 */
+#define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0)
+#define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1)
+#define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2)
+#define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3)
+#define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_ID(11, 4)
+#define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5)
+#define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6)
+#define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7)
+#define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8)
+#define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9)
+#define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10)
+#define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11)
+#define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12)
+#define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13)
+#define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14)
+#define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15)
+#define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16)
+#define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17)
+#define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18)
+#define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19)
+#define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20)
+#define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21)
+#define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22)
+#define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23)
+#define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24)
+#define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25)
+
+/* larb12: null */
+
+/* larb13 */
+#define M4U_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0)
+#define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_ID(13, 1)
+#define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_ID(13, 2)
+#define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_ID(13, 3)
+#define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_ID(13, 4)
+#define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_ID(13, 5)
+#define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_ID(13, 6)
+#define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_ID(13, 7)
+#define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_ID(13, 8)
+#define M4U_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9)
+#define M4U_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10)
+#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11)
+
+/* larb14 */
+#define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_ID(14, 0)
+#define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_ID(14, 1)
+#define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_ID(14, 2)
+#define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_ID(14, 3)
+#define M4U_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4)
+#define M4U_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5)
+
+/* larb15: null */
+
+/* larb16 */
+#define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0)
+#define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1)
+#define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2)
+#define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3)
+#define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4)
+#define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5)
+#define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6)
+#define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7)
+#define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8)
+#define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9)
+#define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10)
+#define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11)
+#define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12)
+#define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13)
+#define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14)
+#define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15)
+#define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16)
+
+/* larb17 */
+#define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0)
+#define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1)
+#define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2)
+#define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3)
+#define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4)
+#define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5)
+#define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6)
+#define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7)
+#define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8)
+#define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9)
+#define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10)
+#define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11)
+#define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12)
+#define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13)
+#define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14)
+#define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15)
+#define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16)
+
+/* larb18 */
+#define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_ID(18, 0)
+#define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_ID(18, 1)
+#define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_ID(18, 2)
+#define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_ID(18, 3)
+#define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_ID(18, 4)
+#define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_ID(18, 5)
+#define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_ID(18, 6)
+#define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_ID(18, 7)
+#define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_ID(18, 8)
+#define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_ID(18, 9)
+#define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_ID(18, 10)
+#define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_ID(18, 11)
+#define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_ID(18, 12)
+#define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_ID(18, 13)
+#define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_ID(18, 14)
+#define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_ID(18, 15)
+#define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_ID(18, 16)
+
+/* larb19 */
+#define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0)
+#define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1)
+#define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2)
+#define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3)
+
+/* larb20 */
+#define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0)
+#define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1)
+#define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2)
+#define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3)
+#define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4)
+#define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5)
+
+#endif
diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h
new file mode 100644
index 000000000000..7d64103209af
--- /dev/null
+++ b/include/dt-bindings/memory/mtk-memory-port.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_
+#define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_
+
+#define MTK_LARB_NR_MAX 32
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f)
+#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
+
+#endif