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authorMilo Kim <woogyom.kim@gmail.com>2016-11-15 22:02:13 +0900
committerLee Jones <lee.jones@linaro.org>2016-11-29 08:21:39 +0000
commit6d2c2b9f806a4ec81833af533d57395db856d5a3 (patch)
treeb79c7d99b2bcb11901f2a2a4fa055ea7333fd56a /include/linux/mfd/tps65217.h
parentf66020640367affd8efa788dc3f904acac435244 (diff)
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mfd: tps65217: Update register interrupt mask bits instead of writing operation
TPS65217 interrupt register includes read/writeable mask bits with read-only status bits. (bit 4, 5, 6 are R/W, bit 0, 1, 2 are RO) And reserved bit is not required. Register update operation is preferred for disabling all interrupts during the device initialisation. Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'include/linux/mfd/tps65217.h')
-rw-r--r--include/linux/mfd/tps65217.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
index 4ccda8969639..dfa9f0d0ae2b 100644
--- a/include/linux/mfd/tps65217.h
+++ b/include/linux/mfd/tps65217.h
@@ -73,13 +73,14 @@
#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
#define TPS65217_PPATH_USB_CURRENT_MASK 0x03
-#define TPS65217_INT_RESERVEDM BIT(7)
#define TPS65217_INT_PBM BIT(6)
#define TPS65217_INT_ACM BIT(5)
#define TPS65217_INT_USBM BIT(4)
#define TPS65217_INT_PBI BIT(2)
#define TPS65217_INT_ACI BIT(1)
#define TPS65217_INT_USBI BIT(0)
+#define TPS65217_INT_MASK (TPS65217_INT_PBM | TPS65217_INT_ACM | \
+ TPS65217_INT_USBM)
#define TPS65217_CHGCONFIG0_TREG BIT(7)
#define TPS65217_CHGCONFIG0_DPPM BIT(6)