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authorZhiwu Song <zhiwu.song@csr.com>2011-08-30 19:20:34 -0700
committerBarry Song <21cnbao@gmail.com>2011-09-11 09:17:53 +0800
commit684f741446f7a3108b4c167faf20214c42b7eeac (patch)
tree7d6b2d4919640170f61aaaf5460e9b2a6dbb24cd /include/linux/rtc
parent858ba703e842f4ece6680b45862ee9e6e6297d1e (diff)
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ARM: CSR: add rtc i/o bridge interface for SiRFprimaII
The module is a bridge between the RTC clock domain and the CPU interface clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through this module. Signed-off-by: Zhiwu Song <zhiwu.song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/linux/rtc')
-rw-r--r--include/linux/rtc/sirfsoc_rtciobrg.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/include/linux/rtc/sirfsoc_rtciobrg.h b/include/linux/rtc/sirfsoc_rtciobrg.h
new file mode 100644
index 000000000000..2c92e1c8e055
--- /dev/null
+++ b/include/linux/rtc/sirfsoc_rtciobrg.h
@@ -0,0 +1,18 @@
+/*
+ * RTC I/O Bridge interfaces for CSR SiRFprimaII
+ * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#ifndef _SIRFSOC_RTC_IOBRG_H_
+#define _SIRFSOC_RTC_IOBRG_H_
+
+extern void sirfsoc_rtc_iobrg_besyncing(void);
+
+extern u32 sirfsoc_rtc_iobrg_readl(u32 addr);
+
+extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr);
+
+#endif