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authorMattias Nilsson <mattias.i.nilsson@stericsson.com>2012-01-13 16:20:28 +0100
committerSamuel Ortiz <sameo@linux.intel.com>2012-03-06 18:46:32 +0100
commit6b6fae2b890826c99f9e62cceec4f859c98ee575 (patch)
treeacec177001f40c9cc21454e0b140454026f5fd60 /include/linux
parent0508901ca794d411efb09befb88b8194d8387428 (diff)
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mfd: db8500 clock handling update
This updates the clock handling in the DB8500 PRCMU driver with the latest findings and API changes related to changes in the backing firmware in the PRCMU. - Add the necessary interfaces to get the frequencies of the clocks and set the rate of some of the clocks. - Add support for controlling the clocks PLLSOC0, PLLDSI, DSI0, DSI1 and DSI escape clocks (DSInESCCLK). - Correct the PLLSDI enable/disable sequence by using the DSIPLL_CLAMPI bit. After this we will have the interfaces and code to implement the U8500 clock framework properly. Reviewed-by: Jonas Aberg <jonas.aberg@stericsson.com> Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mfd/dbx500-prcmu.h47
1 files changed, 47 insertions, 0 deletions
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index f73b9d9d2a24..8470c7d7121f 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -80,6 +80,29 @@ enum prcmu_wakeup_index {
#define EPOD_STATE_ON_CLK_OFF 0x03
#define EPOD_STATE_ON 0x04
+/* DB5500 CLKOUT IDs */
+enum {
+ DB5500_CLKOUT0 = 0,
+ DB5500_CLKOUT1,
+};
+
+/* DB5500 CLKOUTx sources */
+enum {
+ DB5500_CLKOUT_REF_CLK_SEL0,
+ DB5500_CLKOUT_RTC_CLK0_SEL0,
+ DB5500_CLKOUT_ULP_CLK_SEL0,
+ DB5500_CLKOUT_STATIC0,
+ DB5500_CLKOUT_REFCLK,
+ DB5500_CLKOUT_ULPCLK,
+ DB5500_CLKOUT_ARMCLK,
+ DB5500_CLKOUT_SYSACC0CLK,
+ DB5500_CLKOUT_SOC0PLLCLK,
+ DB5500_CLKOUT_SOC1PLLCLK,
+ DB5500_CLKOUT_DDRPLLCLK,
+ DB5500_CLKOUT_TVCLK,
+ DB5500_CLKOUT_IRDACLK,
+};
+
/*
* CLKOUT sources
*/
@@ -111,6 +134,7 @@ enum prcmu_clock {
PRCMU_MSP1CLK,
PRCMU_I2CCLK,
PRCMU_SDMMCCLK,
+ PRCMU_SPARE1CLK,
PRCMU_SLIMCLK,
PRCMU_PER1CLK,
PRCMU_PER2CLK,
@@ -139,12 +163,20 @@ enum prcmu_clock {
PRCMU_IRRCCLK,
PRCMU_SIACLK,
PRCMU_SVACLK,
+ PRCMU_ACLK,
PRCMU_NUM_REG_CLOCKS,
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
+ PRCMU_CDCLK,
PRCMU_TIMCLK,
PRCMU_PLLSOC0,
PRCMU_PLLSOC1,
PRCMU_PLLDDR,
+ PRCMU_PLLDSI,
+ PRCMU_DSI0CLK,
+ PRCMU_DSI1CLK,
+ PRCMU_DSI0ESCCLK,
+ PRCMU_DSI1ESCCLK,
+ PRCMU_DSI2ESCCLK,
};
/**
@@ -516,6 +548,21 @@ static inline int prcmu_request_clock(u8 clock, bool enable)
return 0;
}
+static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
+{
+ return 0;
+}
+
+static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
+{
+ return 0;
+}
+
+static inline unsigned long prcmu_clock_rate(u8 clock)
+{
+ return 0;
+}
+
static inline int prcmu_set_ape_opp(u8 opp)
{
return 0;