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author | Dave Airlie <airlied@redhat.com> | 2019-12-27 15:25:04 +1000 |
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committer | Dave Airlie <airlied@redhat.com> | 2019-12-27 15:25:04 +1000 |
commit | 3ae3271443b337c1cd421a9b73d51c5c2de52977 (patch) | |
tree | 2ce6c36149f45e50af5b3c321fa2b5222f9b81ae /include/uapi/drm | |
parent | 5f773e551a3b977013df24d570d486645f326672 (diff) | |
parent | 3446c63a0f2a691fdc6fffaddc6e0c1285efc80c (diff) | |
download | linux-3ae3271443b337c1cd421a9b73d51c5c2de52977.tar.gz linux-3ae3271443b337c1cd421a9b73d51c5c2de52977.tar.bz2 linux-3ae3271443b337c1cd421a9b73d51c5c2de52977.zip |
Merge tag 'drm-intel-next-2019-12-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
i915 features for v5.6:
- Separate hardware and uapi state (Maarten)
- Expose a number of sprite and plane formats (Ville)
- DDC symlink in HDMI connector sysfs directory (Andrzej Pietrasiewicz)
- Improve obj->mm.lock nesting lock annotation (Daniel)
(Includes lockdep changes)
- Selftest improvements across the board (Chris)
- ICL/TGL VDSC support on DSI (Jani, Vandita)
- TGL DSB fixes (Animesh, Lucas, Tvrtko)
- VBT parsing improvements and fixes (Lucas, Matt, José, Jani, Dan Carpenter)
- Fix LPSS vs. PMIC PWM backlight use on BYT/CHT (Hans)
(Includes ACPI+MFD changes)
- Display state, crtc, plane code refactoring (Ville)
- Set opregion chpd value to indicate the driver handles hotplug (Hans de Goede)
- DSI updates and fixes, TGL pipe D support, port mapping (José, Jani, Vandita)
- Make HDCP 2.2 support cover CFL (Juston Li)
- Fix CML PCI IDs and ULT (Shawn Lee)
- CMP-V PCH fix (Imre)
- TGL: Add another TGL PCH ID (James)
- EHL/JSL: Add new PCI IDs (James)
- Rename pipe update tracepoints (Ville)
- Fix FBC on GLK+ (Ville)
- GuC fixes and improvements (Daniele, Don Hiatt, Stuart Summers, Matthew Brost)
- Display debugfs improvements (Ville)
- Hotplug/irq fixes (Matt)
- PSR fixes and improvements (José)
- DRM_I915_GEM_MMAP_OFFSET ioctl (Abdiel)
- Static analysis fixes (Colin Ian King)
- Register sysctl path globally (Venkata Sandeep Dhanalakota)
- Introduce new macros for tracing (Venkata Sandeep Dhanalakota)
- Migrate gt towards intel_uncore_read/write (Andi)
- Add rps frequency translation helpers (Andi)
- Fix TGL transcoder clock off sequence (José)
- Fix TGL port A audio (Kai Vehmanen)
- TGL render decompression (DK)
- GEM/GT improvements and fixes across the board (Chris)
- Couple of backmerges (Jani)
Signed-off-by: Dave Airlie <airlied@redhat.com>
# gpg: Signature made Tue 24 Dec 2019 03:20:48 AM AEST
# gpg: using RSA key D398079D26ABEE6F
# gpg: Good signature from "Jani Nikula <jani.nikula@intel.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1565 A65B 77B0 632E 1124 E59C D398 079D 26AB EE6F
# Conflicts:
# drivers/gpu/drm/i915/display/intel_fbc.c
# drivers/gpu/drm/i915/gt/intel_lrc.c
# drivers/gpu/drm/i915/i915_gem.c
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87lfr3rkry.fsf@intel.com
Diffstat (limited to 'include/uapi/drm')
-rw-r--r-- | include/uapi/drm/drm_fourcc.h | 11 | ||||
-rw-r--r-- | include/uapi/drm/i915_drm.h | 32 |
2 files changed, 43 insertions, 0 deletions
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 8caaaf7ff91b..5ba481f49931 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -411,6 +411,17 @@ extern "C" { #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) /* + * Intel color control surfaces (CCS) for Gen-12 render compression. + * + * The main surface is Y-tiled and at plane index 0, the CCS is linear and + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in + * main surface. In other words, 4 bits in CCS map to a main surface cache + * line pair. The main surface pitch is required to be a multiple of four + * Y-tile widths. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) + +/* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * * Macroblocks are laid in a Z-shape, and each pixel data is following the diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 5400d7e057f1..829c0a48577f 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -395,6 +395,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) +#define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) @@ -793,6 +794,37 @@ struct drm_i915_gem_mmap_gtt { __u64 offset; }; +struct drm_i915_gem_mmap_offset { + /** Handle for the object being mapped. */ + __u32 handle; + __u32 pad; + /** + * Fake offset to use for subsequent mmap call + * + * This is a fixed-size type for 32/64 compatibility. + */ + __u64 offset; + + /** + * Flags for extended behaviour. + * + * It is mandatory that one of the MMAP_OFFSET types + * (GTT, WC, WB, UC, etc) should be included. + */ + __u64 flags; +#define I915_MMAP_OFFSET_GTT 0 +#define I915_MMAP_OFFSET_WC 1 +#define I915_MMAP_OFFSET_WB 2 +#define I915_MMAP_OFFSET_UC 3 + + /* + * Zero-terminated chain of extensions. + * + * No current extensions defined; mbz. + */ + __u64 extensions; +}; + struct drm_i915_gem_set_domain { /** Handle for the object */ __u32 handle; |