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| author | Bjorn Helgaas <bhelgaas@google.com> | 2024-05-16 18:14:09 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-05-16 18:14:09 -0500 |
| commit | 83711a1ab210cf59d30a3e65f72268f5404c1870 (patch) | |
| tree | 65f9202cc2aa46c84b87f4c4f71d76eb3f388f01 /include/uapi/linux/pci_regs.h | |
| parent | a6faf3f450ecdb084128751e8fda0e515283da39 (diff) | |
| parent | 934edcd436dca0447e0d3691a908394ba16d06c3 (diff) | |
| download | linux-83711a1ab210cf59d30a3e65f72268f5404c1870.tar.gz linux-83711a1ab210cf59d30a3e65f72268f5404c1870.tar.bz2 linux-83711a1ab210cf59d30a3e65f72268f5404c1870.zip | |
Merge branch 'pci/cxl'
- Lock the upstream bridge while using it to perform a Secondary Bus Reset
(Dave Jiang)
- Return failure when attempting Secondary Bus Reset below a CXL Port that
has SBR masked (Dave Jiang)
- Add a "cxl_bus" reset method that temporarily unmasks SBR (Dave Jiang)
- Add a warning if we reset a CXL type 3 memory device that was in use
while being reset (Dave Jiang)
* pci/cxl:
cxl: Add post-reset warning if reset results in loss of previously committed HDM decoders
PCI/CXL: Add 'cxl_bus' reset method for devices below CXL Ports
PCI/CXL: Fail bus reset if upstream CXL Port has SBR masked
PCI: Lock upstream bridge for pci_reset_function()
PCI/CXL: Move CXL Vendor ID to pci_ids.h
Diffstat (limited to 'include/uapi/linux/pci_regs.h')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index a39193213ff2..6024eb2e9a2f 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1148,4 +1148,9 @@ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 +/* Compute Express Link (CXL r3.1, sec 8.1.5) */ +#define PCI_DVSEC_CXL_PORT 3 +#define PCI_DVSEC_CXL_PORT_CTL 0x0c +#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 + #endif /* LINUX_PCI_REGS_H */ |