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authorDave Airlie <airlied@redhat.com>2013-09-28 14:45:30 +1000
committerDave Airlie <airlied@redhat.com>2013-09-28 14:45:30 +1000
commit41ed7fe92f17ab8d29e9c6ccf0679ba522552992 (patch)
tree3fcc37d6e526a52d8b0606e980dbc78771a3dbed /include/uapi
parent36dec40cebe3fc9c14639927aad08e21168154cc (diff)
parent58d327da9721f7a0f6e46c8dfa5cc5546fd7078a (diff)
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Merge branch 'drm-fixes-3.12' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
More radeon fixes for 3.12. Kind of all over the place: UVD, DPM, tiling, etc. * 'drm-fixes-3.12' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: fix hdmi audio on DCE3.0/3.1 asics drm/radeon/cik: fix overflow in vram fetch drm/radeon: add missing hdmi callbacks for rv6xx drm/radeon/uvd: lower msg&fb buffer requirements on UVD3 drm/radeon: disable tests/benchmarks if accel is disabled drm/radeon: don't set default clocks for SI when DPM is disabled drm/radeon/dpm/ci: filter clocks based on voltage/clk dep tables drm/radeon/dpm/si: filter clocks based on voltage/clk dep tables drm/radeon/dpm/ni: filter clocks based on voltage/clk dep tables drm/radeon/dpm/btc: filter clocks based on voltage/clk dep tables drm/radeon/dpm: fetch the max clk from voltage dep tables helper drm/radeon: fix missed variable sized access drm/radeon: Make r100_cp_ring_info() and radeon_ring_gfx() safe (v2) drm/radeon/cik: Add tiling mode index for 1D tiled depth/stencil surfaces drm/radeon/cik: Fix encoding of number of banks in tiling configuration info drm/radeon/cik: Fix printing of client name on VM protection fault drm/radeon: additional gcc fixes for radeon_atombios.c drm/radeon: avoid UVD corruption on AGP cards using GPU gart
Diffstat (limited to 'include/uapi')
-rw-r--r--include/uapi/drm/radeon_drm.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index fa8b3adf9ffb..46d41e8b0dcc 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -1007,4 +1007,6 @@ struct drm_radeon_info {
#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
+#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
+
#endif