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| author | Ben Dooks <ben-linux@fluff.org> | 2006-06-27 22:53:04 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-28 17:54:54 +0100 |
| commit | 2b8b4913efa20f76718f524accf40e6d02a3bf0a (patch) | |
| tree | 35f2df1ad0169182d8741a5744141c1a66314077 /include | |
| parent | b8ccca4a57c91dfd81b0a50e16942699bb01600a (diff) | |
| download | linux-2b8b4913efa20f76718f524accf40e6d02a3bf0a.tar.gz linux-2b8b4913efa20f76718f524accf40e6d02a3bf0a.tar.bz2 linux-2b8b4913efa20f76718f524accf40e6d02a3bf0a.zip | |
[ARM] 3661/1: S3C2412: Fix compilation if CPU_S3C2410 only
Patch from Ben Dooks
If only the S3C2412 based machines are selected,
then the regs-dsc.h does not export the S3C2412_DSC
registers as it is wrapped in CONFIG_CPU_S3C2440.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-dsc.h | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h index 84aca61cbaa3..a0a124875164 100644 --- a/include/asm-arm/arch-s3c2410/regs-dsc.h +++ b/include/asm-arm/arch-s3c2410/regs-dsc.h @@ -7,25 +7,23 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * S3C2440 Signal Drive Strength Control - * - * Changelog: - * 11-Aug-2004 BJD Created file - * 25-Aug-2004 BJD Added the _SELECT_* defs for using with functions + * S3C2440/S3C2412 Signal Drive Strength Control */ #ifndef __ASM_ARCH_REGS_DSC_H #define __ASM_ARCH_REGS_DSC_H "2440-dsc" -#ifdef CONFIG_CPU_S3C2440 +#if defined(CONFIG_CPU_S3C2412) +#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) +#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) +#endif + +#if defined(CONFIG_CPU_S3C2440) #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) -#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) -#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) - #define S3C2440_SELECT_DSC0 (0) #define S3C2440_SELECT_DSC1 (1<<31) |