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| author | Paul Mundt <lethal@linux-sh.org> | 2010-11-30 14:42:55 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-11-30 14:42:55 +0900 |
| commit | d8e7943d821d8ee7f48ff38f6f7c509297c88402 (patch) | |
| tree | 7c3990942d495fd6bdfcdf6e69fe37bda8e4ce33 /include | |
| parent | df73af86b6e737f357aae85e0b5e621516117780 (diff) | |
| parent | 22efa0fee32d9e7f6f6fbc396a872b5708d86048 (diff) | |
| download | linux-d8e7943d821d8ee7f48ff38f6f7c509297c88402.tar.gz linux-d8e7943d821d8ee7f48ff38f6f7c509297c88402.tar.bz2 linux-d8e7943d821d8ee7f48ff38f6f7c509297c88402.zip | |
Merge branch 'common/mmcif' into rmobile/mmcif
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mmc/sh_mmcif.h | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h index f216a8879b58..44fc5348fd5d 100644 --- a/include/linux/mmc/sh_mmcif.h +++ b/include/linux/mmc/sh_mmcif.h @@ -77,6 +77,9 @@ struct sh_mmcif_plat_data { #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) +#define CLKDIV_4 (1<<16) /* mmc clock frequency. + * n: bus clock/(2^(n+1)) */ +#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */ #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */ #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \ (1 << 9) | (1 << 8)) /* resp busy timeout */ @@ -87,7 +90,7 @@ struct sh_mmcif_plat_data { /* CE_VERSION */ #define SOFT_RST_ON (1 << 31) -#define SOFT_RST_OFF ~SOFT_RST_ON +#define SOFT_RST_OFF 0 static inline u32 sh_mmcif_readl(void __iomem *addr, int reg) { @@ -175,12 +178,9 @@ static inline int sh_mmcif_boot_do_read(void __iomem *base, static inline void sh_mmcif_boot_init(void __iomem *base) { - unsigned long tmp; - /* reset */ - tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION); - sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | SOFT_RST_ON); - sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & SOFT_RST_OFF); + sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON); + sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF); /* byte swap */ sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); @@ -188,14 +188,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base) /* Set block size in MMCIF hardware */ sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); - /* Enable the clock, set it to Bus clock/256 (about 325Khz). - * It is unclear where 0x70000 comes from or if it is even needed. - * It is there for byte-compatibility with code that is known to - * work. - */ + /* Enable the clock, set it to Bus clock/256 (about 325Khz). */ sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, - CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | - SCCSTO_29 | 0x70000); + CLK_ENABLE | CLKDIV_256 | SRSPTO_256 | + SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); /* CMD0 */ sh_mmcif_boot_cmd(base, 0x00000040, 0); @@ -220,7 +216,9 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base, unsigned long tmp; /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */ - sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff); + sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, + CLK_ENABLE | CLKDIV_4 | SRSPTO_256 | + SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); /* CMD9 - Get CSD */ sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000); |