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author | Paul Cercueil <paul@crapouillou.net> | 2020-12-12 13:57:33 +0000 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2020-12-19 16:04:58 -0800 |
commit | 11a163f2c7d6a9f27ce144cd7e367a81c851621a (patch) | |
tree | 422228c83974b0020d1fd9c68a89dceb75790909 /kernel | |
parent | 3650b228f83adda7e5ee532e2b90429c03f7b9ec (diff) | |
download | linux-11a163f2c7d6a9f27ce144cd7e367a81c851621a.tar.gz linux-11a163f2c7d6a9f27ce144cd7e367a81c851621a.tar.bz2 linux-11a163f2c7d6a9f27ce144cd7e367a81c851621a.zip |
clk: ingenic: Fix divider calculation with div tables
The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.
Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.
Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables")
Cc: <stable@vger.kernel.org> # 5.2
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions