diff options
| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2014-08-13 12:32:03 +0530 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2014-08-13 18:20:41 +1000 |
| commit | 85c1fafd7262e68ad821ee1808686b1392b1167d (patch) | |
| tree | 9b454eb7a172d0b583f7132527fd3d5098f2defa /lib/crc-t10dif.c | |
| parent | 7e467245bf5226db34c4b12d3cbacfa2f7a15a8b (diff) | |
| download | linux-85c1fafd7262e68ad821ee1808686b1392b1167d.tar.gz linux-85c1fafd7262e68ad821ee1808686b1392b1167d.tar.bz2 linux-85c1fafd7262e68ad821ee1808686b1392b1167d.zip | |
powerpc/mm: Use read barrier when creating real_pte
On ppc64 we support 4K hash pte with 64K page size. That requires
us to track the hash pte slot information on a per 4k basis. We do that
by storing the slot details in the second half of pte page. The pte bit
_PAGE_COMBO is used to indicate whether the second half need to be
looked while building real_pte. We need to use read memory barrier while
doing that so that load of hidx is not reordered w.r.t _PAGE_COMBO
check. On the store side we already do a lwsync in __hash_page_4K
CC: <stable@vger.kernel.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'lib/crc-t10dif.c')
0 files changed, 0 insertions, 0 deletions