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authorTakeshi Kihara <takeshi.kihara.df@renesas.com>2018-02-16 15:25:02 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2018-02-20 19:02:10 +0100
commit740a4a3aa76ed46a425909ba34cc82c4ddb91252 (patch)
tree00f7b9d693354922a792e21ff5333130a0f195f3 /scripts/extract-cert.c
parent65a90f046ba11c5b5cc5f89d732deaa8b08068e2 (diff)
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pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for SSI pins group
This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment for SSI pins group. This is a correction because MOD_SEL register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c8f82 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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