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authorMark Brown <broonie@kernel.org>2025-04-25 18:51:40 +0100
committerMark Brown <broonie@kernel.org>2025-04-25 18:51:40 +0100
commit15cfe55ec58ace931a73e19e5367598734ceb074 (patch)
treee8cfc9db8a2ac81c8ca495ded326dd9e5b8550a7 /scripts/generate_rust_analyzer.py
parent8e4d3d8a5e51e07bd0d6cdd81b5e4af79f796927 (diff)
parent0889c4d28ad79b55ee8cf3c818e9d86203ace8f0 (diff)
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Add basic SPI support for SOPHGO SG2042 SoC
Merge series from Zixian Zeng <sycamoremoon376@gmail.com>: Implemented basic SPI support for SG2042 SoC[1] using the upstreamed Synopsys DW-SPI IP. The way of testing can be found here [2]. Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com> --- Changes in v6: - patch 1: Apply Krzysztof's tag. - patch 2: Adjust enum to alphabetical order. - Link to v5: https://lore.kernel.org/r/20250422-sfg-spi-v5-0-c7f6554a94a0@gmail.com Changes in v5: - patch 1: New patch merges all vendors fall back to snps,dw-apb-ssi into one entry - Link to v4: https://lore.kernel.org/r/20250407-sfg-spi-v4-0-30ac949a1e35@gmail.com Changes in v4: - Adjust the order of spi nodes. - Place the binding after Renesas. - Fix the description issues of patches. - Link to v3: https://lore.kernel.org/r/20250313-sfg-spi-v3-0-e686427314b2@gmail.com Changes in v3: - Remove the spi status on sg2042-milkv-pioneer board. - Remove clock GATE_CLK_SYSDMA_AXI from spi. [3] - Create dt-binding of compatible property. - Replace the general compatible property with SoC-specific in dts. - Link to v2: https://lore.kernel.org/r/20250228-sfg-spi-v2-1-8bbf23b85d0e@gmail.com Changes in v2: - Rebase v1 to sophgo/master(github.com/sophgo/linux.git). - Order properties in device node. - Remove unevaluated properties `clock-frequency`. - Set default status to disable. - Link to v1: https://lore.kernel.org/r/20250228-sfg-spi-v1-1-b989aed94911@gmail.com Link: https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/SPI.rst [1] Link: https://lore.kernel.org/all/CAKyUbwXqg13Ho7QHw8vV2W6OcObphwhQ8HUrZMDNBxrVxLmdug@mail.gmail.com/ [2] Link: https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/clock.rst#clock-tree [3] --- Zixian Zeng (3): spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC riscv: sophgo: dts: Add spi controller for SG2042 .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 19 ++++++---------- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 26 ++++++++++++++++++++++ 2 files changed, 33 insertions(+), 12 deletions(-) --- base-commit: 8ffd015db85fea3e15a77027fda6c02ced4d2444 change-id: 20250228-sfg-spi-e3f2aeca09ab Best regards, -- Zixian Zeng <sycamoremoon376@gmail.com>
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