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authorGrygorii Strashko <grygorii.strashko@ti.com>2020-03-03 18:00:27 +0200
committerKishon Vijay Abraham I <kishon@ti.com>2020-03-20 19:34:29 +0530
commitd9aa91dfb2da59c1f22887013a1cec32a6f9fcec (patch)
tree75686dc3e87a7d145729f73c57e4e25907dba3a8 /scripts/spdxcheck.py
parent74e29703a78c120cd129e2b49ac8213713d2648c (diff)
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phy: ti: gmii-sel: add support for am654x/j721e soc
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding support for TI AM654x/J721E SoCs PHY interface selection. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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