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| author | Finley Xiao <finley.xiao@rock-chips.com> | 2023-11-27 19:14:16 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-11-28 10:30:58 +0100 |
| commit | 98dcc6be3859fb15257750b8e1d4e0eefd2c5e1e (patch) | |
| tree | 993f116b104e46ac7c681f03e7df2fd31bf94352 /tools/perf/scripts/python/gecko.py | |
| parent | c6c5a5580dcb6631aa6369dabe12ef3ce784d1d2 (diff) | |
| download | linux-98dcc6be3859fb15257750b8e1d4e0eefd2c5e1e.tar.gz linux-98dcc6be3859fb15257750b8e1d4e0eefd2c5e1e.tar.bz2 linux-98dcc6be3859fb15257750b8e1d4e0eefd2c5e1e.zip | |
clk: rockchip: rk3128: Fix aclk_peri_src's parent
According to the TRM there are no specific gpll_peri, cpll_peri,
gpll_div2_peri or gpll_div3_peri gates, but a single clk_peri_src gate.
Instead mux_clk_peri_src directly connects to the plls respectively the pll
divider clocks.
Fix this by creating a single gated composite.
Also rename all occurrences of aclk_peri_src to clk_peri_src, since it
is the parent for peri aclks, pclks and hclks. That name also matches
the one used in the TRM.
Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
[renamed aclk_peri_src -> clk_peri_src and added commit message]
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231127181415.11735-4-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/gecko.py')
0 files changed, 0 insertions, 0 deletions