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| author | Zhang Rui <rui.zhang@intel.com> | 2024-03-12 11:19:15 +0800 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2024-04-09 14:04:23 -0400 |
| commit | bb5db22c13125b38b0740e19c18ae94f8e5a0eb6 (patch) | |
| tree | fdeefc75ff626bc11c10f5afcc62bec827e0fa7f /tools/power/x86/turbostat/turbostat.c | |
| parent | 17d1ea136be86f53be0461b0c33daf6b58e6cbf7 (diff) | |
| download | linux-bb5db22c13125b38b0740e19c18ae94f8e5a0eb6.tar.gz linux-bb5db22c13125b38b0740e19c18ae94f8e5a0eb6.tar.bz2 linux-bb5db22c13125b38b0740e19c18ae94f8e5a0eb6.zip | |
tools/power/turbostat: Enable MSR_CORE_C1_RES support for ICX
Enable Core C1 hardware residency counter (MSR_CORE_C1_RES) on ICX.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools/power/x86/turbostat/turbostat.c')
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 283dffb987b5..372f67a70d8a 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -664,6 +664,7 @@ static const struct platform_features icx_features = { .bclk_freq = BCLK_100MHZ, .supported_cstates = CC1 | CC6 | PC2 | PC6, .cst_limit = CST_LIMIT_ICX, + .has_msr_core_c1_res = 1, .has_irtl_msrs = 1, .has_cst_prewake_bit = 1, .trl_msrs = TRL_BASE | TRL_CORECOUNT, |