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| author | Bard Liao <yung-chuan.liao@linux.intel.com> | 2025-02-27 22:06:13 +0800 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2025-03-10 12:31:19 +0530 |
| commit | 3394e2b125043aeede344d28fc73b3c0d2a5c21f (patch) | |
| tree | 7ada884d16282f86e6ad1e7d9d1e692f4d4d3923 /tools/testing/selftests/bpf/prog_tests/autoload.c | |
| parent | 4c1ce9f37d8a809dcdfba082cc9003880efa0a63 (diff) | |
| download | linux-3394e2b125043aeede344d28fc73b3c0d2a5c21f.tar.gz linux-3394e2b125043aeede344d28fc73b3c0d2a5c21f.tar.bz2 linux-3394e2b125043aeede344d28fc73b3c0d2a5c21f.zip | |
ASoC: SOF: Intel: hda-sdw-bpt: add CHAIN_DMA support
When the firmware is involved, the data can be transferred with a
CHAIN_DMA on LNL+.
The CHAIN_DMA needs to be programmed before the DMAs per the
documentation. The states are not exactly symmetrical, on stop we must
do a PAUSE and RESET.
The FIFO size of 10ms was determined experimentally. With the minimum
of 2ms, errors were reported by the codec, likely because of xruns.
The code flow deals with the two TX and RX CHAIN_DMAs in symmetrical
ways, i.e.
alloc TX
alloc RX
enable TX
enable RX
disable RX
disable TX
free RX
free TX
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.dev>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Acked-by: Mark Brown <broonie@kernel.org>
Tested-by: shumingf@realtek.com
Link: https://lore.kernel.org/r/20250227140615.8147-15-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/testing/selftests/bpf/prog_tests/autoload.c')
0 files changed, 0 insertions, 0 deletions