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author | Linus Walleij <linus.walleij@linaro.org> | 2020-05-15 15:06:00 +0200 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2020-05-15 15:06:00 +0200 |
commit | 98a09fb4cbb0b1a750259c285b3abe7e67717121 (patch) | |
tree | 7d7f495990d298fceed61ca69f1ad576c0fd0d60 /tools | |
parent | d7faa8ffb6be57bf8233a4b5a636d76b83c51ce7 (diff) | |
parent | 6d649fca349155698ba4b8858b258a62003c5c54 (diff) | |
download | linux-98a09fb4cbb0b1a750259c285b3abe7e67717121.tar.gz linux-98a09fb4cbb0b1a750259c285b3abe7e67717121.tar.bz2 linux-98a09fb4cbb0b1a750259c285b3abe7e67717121.zip |
Merge tag 'intel-pinctrl-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.8-1
* Introduce GPIO driver for Jasper Lake
* Fix long standing bug in Sunrisepoint-H PAD locking code
* Enable pin configuration setting for GPIO chip for Baytrail
* Work around race condition in Cherriview hardware when handle IRQ
* Clean up Cherryview code to be closer to other drivers
The following is an automated git shortlog grouped by driver:
baytrail:
- Use platform_get_irq_optional() explicitly
- Enable pin configuration setting for GPIO chip
cannonlake:
- Use generic flag for special GPIO base treatment
cherryview:
- Add missing spinlock usage in chv_gpio_irq_handler
- Use GENMASK() consistently
- Re-use data structures from pinctrl-intel.h (part 2)
icelake:
- Use generic flag for special GPIO base treatment
intel:
- Move npins closer to pin_base in struct intel_community
- Update description in struct intel_community
- Add Intel Jasper Lake pin controller support
- Introduce new flag to force GPIO base to be 0
- Introduce common flags for GPIO mapping scheme
lynxpoint:
- Use platform_get_irq_optional() explicitly
sunrisepoint:
- Fix PAD lock register offset for SPT-H
tigerlake:
- Use generic flag for special GPIO base treatment
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions