diff options
26 files changed, 457 insertions, 761 deletions
diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documentation/devicetree/bindings/net/dsa/dsa.yaml index 2abd036578d1..6107189d276a 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -46,10 +46,4 @@ $defs: $ref: dsa-port.yaml# unevaluatedProperties: false -oneOf: - - required: - - ports - - required: - - ethernet-ports - ... diff --git a/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml b/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml deleted file mode 100644 index 4f1adf00431a..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml +++ /dev/null @@ -1,88 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6060.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Marvell MV88E6060 DSA switch - -maintainers: - - Andrew Lunn <andrew@lunn.ch> - -description: - The Marvell MV88E6060 switch has been produced and sold by Marvell - since at least 2008. The switch has one pin ADDR4 that controls the - MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus - connected to the switch, the PHYs inside the switch appear as - independent devices on address 0x00-0x04 or 0x10-0x14, so in difference - from many other DSA switches this switch does not have an internal - MDIO bus for the PHY devices. - -properties: - compatible: - const: marvell,mv88e6060 - description: - The MV88E6060 is the oldest Marvell DSA switch product, and - as such a bit limited in features compared to later hardware. - - reg: - maxItems: 1 - - reset-gpios: - description: - GPIO to be used to reset the whole device - maxItems: 1 - -allOf: - - $ref: dsa.yaml#/$defs/ethernet-ports - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/interrupt-controller/irq.h> - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethernet-switch@16 { - compatible = "marvell,mv88e6060"; - reg = <16>; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - ethernet-port@0 { - reg = <0>; - label = "lan1"; - }; - ethernet-port@1 { - reg = <1>; - label = "lan2"; - }; - ethernet-port@2 { - reg = <2>; - label = "lan3"; - }; - ethernet-port@3 { - reg = <3>; - label = "lan4"; - }; - ethernet-port@5 { - reg = <5>; - phy-mode = "rev-mii"; - ethernet = <ðc>; - fixed-link { - speed = <100>; - full-duplex; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml b/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml deleted file mode 100644 index 34d8561a2187..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml +++ /dev/null @@ -1,330 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Marvell MV88E6xxx DSA switch family - -maintainers: - - Andrew Lunn <andrew@lunn.ch> - -description: - The Marvell MV88E6xxx switch series has been produced and sold - by Marvell since at least 2008. The switch has a few compatibles which - just indicate the base address of the switch, then operating systems - can investigate switch ID registers to find out which actual version - of the switch it is dealing with. - -properties: - compatible: - enum: - - marvell,mv88e6085 - - marvell,mv88e6190 - - marvell,mv88e6250 - description: | - marvell,mv88e6085: This switch uses base address 0x10. - This switch and its siblings will be autodetected from - ID registers found in the switch, so only "marvell,mv88e6085" should be - specified. This includes the following list of MV88Exxxx switches: - 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, 6171, 6172, 6175, 6176, - 6185, 6240, 6320, 6321, 6341, 6350, 6351, 6352 - marvell,mv88e6190: This switch uses base address 0x00. - This switch and its siblings will be autodetected from - ID registers found in the switch, so only "marvell,mv88e6190" should be - specified. This includes the following list of MV88Exxxx switches: - 6190, 6190X, 6191, 6290, 6361, 6390, 6390X - marvell,mv88e6250: This switch uses base address 0x08 or 0x18. - This switch and its siblings will be autodetected from - ID registers found in the switch, so only "marvell,mv88e6250" should be - specified. This includes the following list of MV88Exxxx switches: - 6220, 6250 - - reg: - maxItems: 1 - - eeprom-length: - $ref: /schemas/types.yaml#/definitions/uint32 - description: Set to the length of an EEPROM connected to the switch. Must be - set if the switch can not detect the presence and/or size of a connected - EEPROM, otherwise optional. - - reset-gpios: - description: - GPIO to be used to reset the whole device - maxItems: 1 - - interrupts: - description: The switch provides an external interrupt line, but it is - not always used by target systems. - maxItems: 1 - - interrupt-controller: - description: The switch has an internal interrupt controller used by - the different sub-blocks. - - '#interrupt-cells': - description: The internal interrupt controller only supports triggering - on active high level interrupts so the second cell must alway be set to - IRQ_TYPE_LEVEL_HIGH. - const: 2 - - mdio: - $ref: /schemas/net/mdio.yaml# - unevaluatedProperties: false - description: Marvell MV88E6xxx switches have an varying combination of - internal and external MDIO buses, in some cases a combined bus that - can be used both internally and externally. This node is for the - primary bus, used internally and sometimes also externally. - - mdio-external: - $ref: /schemas/net/mdio.yaml# - unevaluatedProperties: false - description: Marvell MV88E6xxx switches that have a separate external - MDIO bus use this port to access external components on the MDIO bus. - - properties: - compatible: - const: marvell,mv88e6xxx-mdio-external - - required: - - compatible - -allOf: - - $ref: dsa.yaml#/$defs/ethernet-ports - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - #include <dt-bindings/gpio/gpio.h> - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethernet-switch@0 { - compatible = "marvell,mv88e6085"; - reg = <0>; - reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - sw_phy0: ethernet-phy@0 { - reg = <0x0>; - }; - - sw_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - - sw_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - - sw_phy3: ethernet-phy@3 { - reg = <0x3>; - }; - }; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - ethernet-port@0 { - reg = <0>; - label = "lan4"; - phy-handle = <&sw_phy0>; - phy-mode = "internal"; - }; - - ethernet-port@1 { - reg = <1>; - label = "lan3"; - phy-handle = <&sw_phy1>; - phy-mode = "internal"; - }; - - ethernet-port@2 { - reg = <2>; - label = "lan2"; - phy-handle = <&sw_phy2>; - phy-mode = "internal"; - }; - - ethernet-port@3 { - reg = <3>; - label = "lan1"; - phy-handle = <&sw_phy3>; - phy-mode = "internal"; - }; - - ethernet-port@5 { - reg = <5>; - ethernet = <&fec>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; - - | - #include <dt-bindings/interrupt-controller/irq.h> - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethernet-switch@0 { - compatible = "marvell,mv88e6190"; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&switch_interrupt_pins>; - pinctrl-names = "default"; - reg = <0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1: ethernet-phy@1 { - reg = <0x1>; - }; - - switch0phy2: ethernet-phy@2 { - reg = <0x2>; - }; - - switch0phy3: ethernet-phy@3 { - reg = <0x3>; - }; - - switch0phy4: ethernet-phy@4 { - reg = <0x4>; - }; - - switch0phy5: ethernet-phy@5 { - reg = <0x5>; - }; - - switch0phy6: ethernet-phy@6 { - reg = <0x6>; - }; - - switch0phy7: ethernet-phy@7 { - reg = <0x7>; - }; - - switch0phy8: ethernet-phy@8 { - reg = <0x8>; - }; - }; - - mdio-external { - compatible = "marvell,mv88e6xxx-mdio-external"; - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@b { - reg = <0xb>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - phy2: ethernet-phy@c { - reg = <0xc>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - ethernet-port@0 { - ethernet = <ð0>; - phy-mode = "rgmii"; - reg = <0>; - - fixed-link { - full-duplex; - pause; - speed = <1000>; - }; - }; - - ethernet-port@1 { - label = "lan1"; - phy-handle = <&switch0phy1>; - reg = <1>; - }; - - ethernet-port@2 { - label = "lan2"; - phy-handle = <&switch0phy2>; - reg = <2>; - }; - - ethernet-port@3 { - label = "lan3"; - phy-handle = <&switch0phy3>; - reg = <3>; - }; - - ethernet-port@4 { - label = "lan4"; - phy-handle = <&switch0phy4>; - reg = <4>; - }; - - ethernet-port@5 { - label = "lan5"; - phy-handle = <&switch0phy5>; - reg = <5>; - }; - - ethernet-port@6 { - label = "lan6"; - phy-handle = <&switch0phy6>; - reg = <6>; - }; - - ethernet-port@7 { - label = "lan7"; - phy-handle = <&switch0phy7>; - reg = <7>; - }; - - ethernet-port@8 { - label = "lan8"; - phy-handle = <&switch0phy8>; - reg = <8>; - }; - - ethernet-port@9 { - /* 88X3310P external phy */ - label = "lan9"; - phy-handle = <&phy1>; - phy-mode = "xaui"; - reg = <9>; - }; - - ethernet-port@a { - /* 88X3310P external phy */ - label = "lan10"; - phy-handle = <&phy2>; - phy-mode = "xaui"; - reg = <0xa>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt new file mode 100644 index 000000000000..6ec0c181b6db --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt @@ -0,0 +1,109 @@ +Marvell DSA Switch Device Tree Bindings +--------------------------------------- + +WARNING: This binding is currently unstable. Do not program it into a +FLASH never to be changed again. Once this binding is stable, this +warning will be removed. + +If you need a stable binding, use the old dsa.txt binding. + +Marvell Switches are MDIO devices. The following properties should be +placed as a child node of an mdio device. + +The properties described here are those specific to Marvell devices. +Additional required and optional properties can be found in dsa.txt. + +The compatibility string is used only to find an identification register, +which is at a different MDIO base address in different switch families. +- "marvell,mv88e6085" : Switch has base address 0x10. Use with models: + 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, + 6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321, + 6341, 6350, 6351, 6352 +- "marvell,mv88e6190" : Switch has base address 0x00. Use with models: + 6190, 6190X, 6191, 6290, 6361, 6390, 6390X +- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model: + 6220, 6250 + +Required properties: +- compatible : Should be one of "marvell,mv88e6085", + "marvell,mv88e6190" or "marvell,mv88e6250" as + indicated above +- reg : Address on the MII bus for the switch. + +Optional properties: + +- reset-gpios : Should be a gpio specifier for a reset line +- interrupts : Interrupt from the switch +- interrupt-controller : Indicates the switch is itself an interrupt + controller. This is used for the PHY interrupts. +#interrupt-cells = <2> : Controller uses two cells, number and flag +- eeprom-length : Set to the length of an EEPROM connected to the + switch. Must be set if the switch can not detect + the presence and/or size of a connected EEPROM, + otherwise optional. +- mdio : Container of PHY and devices on the switches MDIO + bus. +- mdio? : Container of PHYs and devices on the external MDIO + bus. The node must contains a compatible string of + "marvell,mv88e6xxx-mdio-external" + +Example: + + mdio { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + switch0: switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + switch1phy0: switch1phy0@0 { + reg = <0>; + interrupt-parent = <&switch0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + switch0: switch@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + switch1phy0: switch1phy0@0 { + reg = <0>; + interrupt-parent = <&switch0>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + mdio1 { + compatible = "marvell,mv88e6xxx-mdio-external"; + #address-cells = <1>; + #size-cells = <0>; + switch1phy9: switch1phy0@9 { + reg = <9>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/marvell,mvusb.yaml b/Documentation/devicetree/bindings/net/marvell,mvusb.yaml index ab838c1ffeed..3a3325168048 100644 --- a/Documentation/devicetree/bindings/net/marvell,mvusb.yaml +++ b/Documentation/devicetree/bindings/net/marvell,mvusb.yaml @@ -50,14 +50,11 @@ examples: #address-cells = <1>; #size-cells = <0>; - ethernet-switch@0 { + switch@0 { compatible = "marvell,mv88e6190"; reg = <0x0>; - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - + ports { /* Port definitions */ }; diff --git a/MAINTAINERS b/MAINTAINERS index b66dfd9e23b4..b2f53d5cae06 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12626,8 +12626,7 @@ MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER M: Andrew Lunn <andrew@lunn.ch> L: netdev@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml -F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml +F: Documentation/devicetree/bindings/net/dsa/marvell.txt F: Documentation/networking/devlink/mv88e6xxx.rst F: drivers/net/dsa/mv88e6xxx/ F: include/linux/dsa/mv88e6xxx.h diff --git a/arch/arm/boot/dts/marvell/armada-370-rd.dts b/arch/arm/boot/dts/marvell/armada-370-rd.dts index 1b241da11e94..b459a670f615 100644 --- a/arch/arm/boot/dts/marvell/armada-370-rd.dts +++ b/arch/arm/boot/dts/marvell/armada-370-rd.dts @@ -149,37 +149,39 @@ }; }; - switch: ethernet-switch@10 { + switch: switch@10 { compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; reg = <0x10>; interrupt-controller; #interrupt-cells = <2>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; label = "lan0"; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "lan1"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "lan2"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "lan3"; }; - ethernet-port@5 { + port@5 { reg = <5>; ethernet = <ð1>; phy-mode = "rgmii-id"; @@ -194,25 +196,25 @@ #address-cells = <1>; #size-cells = <0>; - switchphy0: ethernet-phy@0 { + switchphy0: switchphy@0 { reg = <0>; interrupt-parent = <&switch>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; }; - switchphy1: ethernet-phy@1 { + switchphy1: switchphy@1 { reg = <1>; interrupt-parent = <&switch>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; - switchphy2: ethernet-phy@2 { + switchphy2: switchphy@2 { reg = <2>; interrupt-parent = <&switch>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; }; - switchphy3: ethernet-phy@3 { + switchphy3: switchphy@3 { reg = <3>; interrupt-parent = <&switch>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts index 5baf83e5253d..f4c4b213ef4e 100644 --- a/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts +++ b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts @@ -77,49 +77,51 @@ pinctrl-0 = <&mdio_pins>; status = "okay"; - ethernet-switch@0 { + switch@0 { compatible = "marvell,mv88e6190"; + #address-cells = <1>; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gpio1>; interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&switch_interrupt_pins>; pinctrl-names = "default"; + #size-cells = <0>; reg = <0>; mdio { #address-cells = <1>; #size-cells = <0>; - switch0phy1: ethernet-phy@1 { + switch0phy1: switch0phy1@1 { reg = <0x1>; }; - switch0phy2: ethernet-phy@2 { + switch0phy2: switch0phy2@2 { reg = <0x2>; }; - switch0phy3: ethernet-phy@3 { + switch0phy3: switch0phy3@3 { reg = <0x3>; }; - switch0phy4: ethernet-phy@4 { + switch0phy4: switch0phy4@4 { reg = <0x4>; }; - switch0phy5: ethernet-phy@5 { + switch0phy5: switch0phy5@5 { reg = <0x5>; }; - switch0phy6: ethernet-phy@6 { + switch0phy6: switch0phy6@6 { reg = <0x6>; }; - switch0phy7: ethernet-phy@7 { + switch0phy7: switch0phy7@7 { reg = <0x7>; }; - switch0phy8: ethernet-phy@8 { + switch0phy8: switch0phy8@8 { reg = <0x8>; }; }; @@ -140,11 +142,11 @@ }; }; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { ethernet = <ð0>; phy-mode = "rgmii"; reg = <0>; @@ -156,55 +158,55 @@ }; }; - ethernet-port@1 { + port@1 { label = "lan1"; phy-handle = <&switch0phy1>; reg = <1>; }; - ethernet-port@2 { + port@2 { label = "lan2"; phy-handle = <&switch0phy2>; reg = <2>; }; - ethernet-port@3 { + port@3 { label = "lan3"; phy-handle = <&switch0phy3>; reg = <3>; }; - ethernet-port@4 { + port@4 { label = "lan4"; phy-handle = <&switch0phy4>; reg = <4>; }; - ethernet-port@5 { + port@5 { label = "lan5"; phy-handle = <&switch0phy5>; reg = <5>; }; - ethernet-port@6 { + port@6 { label = "lan6"; phy-handle = <&switch0phy6>; reg = <6>; }; - ethernet-port@7 { + port@7 { label = "lan7"; phy-handle = <&switch0phy7>; reg = <7>; }; - ethernet-port@8 { + port@8 { label = "lan8"; phy-handle = <&switch0phy8>; reg = <8>; }; - ethernet-port@9 { + port@9 { /* 88X3310P external phy */ label = "lan9"; phy-handle = <&phy1>; @@ -212,7 +214,7 @@ reg = <9>; }; - ethernet-port@a { + port@a { /* 88X3310P external phy */ label = "lan10"; phy-handle = <&phy2>; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 1707d1b01545..1990f7d0cc79 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -7,66 +7,66 @@ }; &mdio { - switch0: ethernet-switch@4 { + switch0: switch0@4 { compatible = "marvell,mv88e6190"; reg = <4>; pinctrl-names = "default"; pinctrl-0 = <&cf_gtr_switch_reset_pins>; reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <1>; label = "lan8"; phy-handle = <&switch0phy0>; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "lan7"; phy-handle = <&switch0phy1>; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "lan6"; phy-handle = <&switch0phy2>; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "lan5"; phy-handle = <&switch0phy3>; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "lan4"; phy-handle = <&switch0phy4>; }; - ethernet-port@6 { + port@6 { reg = <6>; label = "lan3"; phy-handle = <&switch0phy5>; }; - ethernet-port@7 { + port@7 { reg = <7>; label = "lan2"; phy-handle = <&switch0phy6>; }; - ethernet-port@8 { + port@8 { reg = <8>; label = "lan1"; phy-handle = <&switch0phy7>; }; - ethernet-port@10 { + port@10 { reg = <10>; phy-mode = "2500base-x"; @@ -83,35 +83,35 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: ethernet-phy@1 { + switch0phy0: switch0phy0@1 { reg = <0x1>; }; - switch0phy1: ethernet-phy@2 { + switch0phy1: switch0phy1@2 { reg = <0x2>; }; - switch0phy2: ethernet-phy@3 { + switch0phy2: switch0phy2@3 { reg = <0x3>; }; - switch0phy3: ethernet-phy@4 { + switch0phy3: switch0phy3@4 { reg = <0x4>; }; - switch0phy4: ethernet-phy@5 { + switch0phy4: switch0phy4@5 { reg = <0x5>; }; - switch0phy5: ethernet-phy@6 { + switch0phy5: switch0phy5@6 { reg = <0x6>; }; - switch0phy6: ethernet-phy@7 { + switch0phy6: switch0phy6@7 { reg = <0x7>; }; - switch0phy7: ethernet-phy@8 { + switch0phy7: switch0phy7@8 { reg = <0x8>; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts index a7678a784c18..b795ad573891 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts @@ -11,42 +11,42 @@ }; &mdio { - switch0: ethernet-switch@4 { + switch0: switch0@4 { compatible = "marvell,mv88e6085"; reg = <4>; pinctrl-names = "default"; pinctrl-0 = <&cf_gtr_switch_reset_pins>; reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <1>; label = "lan2"; phy-handle = <&switch0phy0>; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "lan1"; phy-handle = <&switch0phy1>; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "lan4"; phy-handle = <&switch0phy2>; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "lan3"; phy-handle = <&switch0phy3>; }; - ethernet-port@5 { + port@5 { reg = <5>; phy-mode = "2500base-x"; ethernet = <ð1>; @@ -63,19 +63,19 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: ethernet-phy@11 { + switch0phy0: switch0phy0@11 { reg = <0x11>; }; - switch0phy1: ethernet-phy@12 { + switch0phy1: switch0phy1@12 { reg = <0x12>; }; - switch0phy2: ethernet-phy@13 { + switch0phy2: switch0phy2@13 { reg = <0x13>; }; - switch0phy3: ethernet-phy@14 { + switch0phy3: switch0phy3@14 { reg = <0x14>; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi index 4116ed60f709..fc8216fd9f60 100644 --- a/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi @@ -158,40 +158,42 @@ &mdio { status = "okay"; - ethernet-switch@0 { + switch@0 { compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; label = "lan4"; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "lan3"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "lan2"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "lan1"; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "wan"; }; - ethernet-port@5 { + port@5 { reg = <5>; phy-mode = "sgmii"; ethernet = <ð2>; diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts index 7b755bb4e4e7..2d8d319bec83 100644 --- a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -435,10 +435,12 @@ }; /* Switch MV88E6176 at address 0x10 */ - ethernet-switch@10 { + switch@10 { pinctrl-names = "default"; pinctrl-0 = <&swint_pins>; compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; dsa,member = <0 0>; reg = <0x10>; @@ -446,36 +448,36 @@ interrupt-parent = <&gpio1>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + ports@0 { reg = <0>; label = "lan0"; }; - ethernet-port@1 { + ports@1 { reg = <1>; label = "lan1"; }; - ethernet-port@2 { + ports@2 { reg = <2>; label = "lan2"; }; - ethernet-port@3 { + ports@3 { reg = <3>; label = "lan3"; }; - ethernet-port@4 { + ports@4 { reg = <4>; label = "lan4"; }; - ethernet-port@5 { + ports@5 { reg = <5>; ethernet = <ð1>; phy-mode = "rgmii-id"; @@ -486,7 +488,7 @@ }; }; - ethernet-port@6 { + ports@6 { reg = <6>; ethernet = <ð0>; phy-mode = "rgmii-id"; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts index 3290ccad2374..32c569df142f 100644 --- a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts @@ -92,42 +92,44 @@ &mdio { status = "okay"; - ethernet-switch@4 { + switch@4 { compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; reg = <4>; pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; pinctrl-names = "default"; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; label = "lan5"; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "lan4"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "lan3"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "lan2"; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "lan1"; }; - ethernet-port@5 { + port@5 { reg = <5>; ethernet = <ð1>; phy-mode = "1000base-x"; @@ -138,7 +140,7 @@ }; }; - ethernet-port@6 { + port@6 { /* 88E1512 external phy */ reg = <6>; label = "lan6"; diff --git a/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts index ea859f7ea042..7a0614fd0c93 100644 --- a/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts @@ -265,40 +265,42 @@ &mdio { status = "okay"; - ethernet-switch@0 { + switch@0 { compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; label = "lan4"; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "lan3"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "lan2"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "lan1"; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "internet"; }; - ethernet-port@5 { + port@5 { reg = <5>; phy-mode = "rgmii-id"; ethernet = <ð0>; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts index 7e72f860c3c5..1a19aec8957b 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts @@ -162,7 +162,7 @@ suppress-preamble; status = "okay"; - switch0: ethernet-switch@0 { + switch0: switch0@0 { compatible = "marvell,mv88e6085"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_switch>; @@ -173,26 +173,26 @@ interrupt-controller; #interrupt-cells = <2>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; label = "eth_cu_1000_1"; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "eth_cu_1000_2"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "eth_cu_1000_3"; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "eth_fc_1000_1"; phy-mode = "1000base-x"; @@ -200,7 +200,7 @@ sfp = <&sff>; }; - ethernet-port@6 { + port@6 { reg = <6>; phy-mode = "rmii"; ethernet = <&fec1>; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts index 77492eeea450..df1335492a19 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts @@ -47,17 +47,17 @@ #address-cells = <1>; #size-cells = <0>; - switch0: ethernet-switch@0 { + switch0: switch0@0 { compatible = "marvell,mv88e6190"; reg = <0>; dsa,member = <0 0>; eeprom-length = <65536>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; phy-mode = "rmii"; ethernet = <&fec1>; @@ -68,37 +68,37 @@ }; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "aib2main_1"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "aib2main_2"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "eth_cu_1000_5"; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "eth_cu_1000_6"; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "eth_cu_1000_4"; }; - ethernet-port@6 { + port@6 { reg = <6>; label = "eth_cu_1000_7"; }; - ethernet-port@7 { + port@7 { reg = <7>; label = "modem_pic"; @@ -108,7 +108,7 @@ }; }; - switch0port10: ethernet-port@10 { + switch0port10: port@10 { reg = <10>; label = "dsa"; phy-mode = "xgmii"; @@ -130,32 +130,32 @@ #address-cells = <1>; #size-cells = <0>; - switch1: ethernet-switch@0 { + switch1: switch1@0 { compatible = "marvell,mv88e6190"; reg = <0>; dsa,member = <0 1>; eeprom-length = <65536>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <1>; label = "eth_cu_1000_3"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "eth_cu_100_2"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "eth_cu_100_3"; }; - switch1port9: ethernet-port@9 { + switch1port9: port@9 { reg = <9>; label = "dsa"; phy-mode = "xgmii"; @@ -168,7 +168,7 @@ }; }; - switch1port10: ethernet-port@10 { + switch1port10: port@10 { reg = <10>; label = "dsa"; phy-mode = "xgmii"; @@ -188,17 +188,17 @@ #address-cells = <1>; #size-cells = <0>; - switch2: ethernet-switch@0 { + switch2: switch2@0 { compatible = "marvell,mv88e6190"; reg = <0>; dsa,member = <0 2>; eeprom-length = <65536>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@2 { + port@2 { reg = <2>; label = "eth_fc_1000_2"; phy-mode = "1000base-x"; @@ -206,7 +206,7 @@ sfp = <&sff1>; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "eth_fc_1000_3"; phy-mode = "1000base-x"; @@ -214,7 +214,7 @@ sfp = <&sff2>; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "eth_fc_1000_4"; phy-mode = "1000base-x"; @@ -222,7 +222,7 @@ sfp = <&sff3>; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "eth_fc_1000_5"; phy-mode = "1000base-x"; @@ -230,7 +230,7 @@ sfp = <&sff4>; }; - ethernet-port@6 { + port@6 { reg = <6>; label = "eth_fc_1000_6"; phy-mode = "1000base-x"; @@ -238,7 +238,7 @@ sfp = <&sff5>; }; - ethernet-port@7 { + port@7 { reg = <7>; label = "eth_fc_1000_7"; phy-mode = "1000base-x"; @@ -246,7 +246,7 @@ sfp = <&sff6>; }; - ethernet-port@9 { + port@9 { reg = <9>; label = "eth_fc_1000_1"; phy-mode = "1000base-x"; @@ -254,7 +254,7 @@ sfp = <&sff0>; }; - switch2port10: ethernet-port@10 { + switch2port10: port@10 { reg = <10>; label = "dsa"; phy-mode = "2500base-x"; @@ -276,17 +276,17 @@ #address-cells = <1>; #size-cells = <0>; - switch3: ethernet-switch@0 { + switch3: switch3@0 { compatible = "marvell,mv88e6190"; reg = <0>; dsa,member = <0 3>; eeprom-length = <65536>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@2 { + port@2 { reg = <2>; label = "eth_fc_1000_8"; phy-mode = "1000base-x"; @@ -294,7 +294,7 @@ sfp = <&sff7>; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "eth_fc_1000_9"; phy-mode = "1000base-x"; @@ -302,7 +302,7 @@ sfp = <&sff8>; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "eth_fc_1000_10"; phy-mode = "1000base-x"; @@ -310,7 +310,7 @@ sfp = <&sff9>; }; - switch3port9: ethernet-port@9 { + switch3port9: port@9 { reg = <9>; label = "dsa"; phy-mode = "2500base-x"; @@ -322,7 +322,7 @@ }; }; - switch3port10: ethernet-port@10 { + switch3port10: port@10 { reg = <10>; label = "dsa"; phy-mode = "xgmii"; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts index 2a490464660c..1461804ecaea 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts @@ -123,7 +123,7 @@ suppress-preamble; status = "okay"; - switch0: ethernet-switch@0 { + switch0: switch0@0 { compatible = "marvell,mv88e6190"; pinctrl-0 = <&pinctrl_gpio_switch0>; pinctrl-names = "default"; @@ -134,11 +134,11 @@ interrupt-controller; #interrupt-cells = <2>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; phy-mode = "rmii"; ethernet = <&fec1>; @@ -149,32 +149,32 @@ }; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "eth_cu_1000_1"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "eth_cu_1000_2"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "eth_cu_1000_3"; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "eth_cu_1000_4"; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "eth_cu_1000_5"; }; - ethernet-port@6 { + port@6 { reg = <6>; label = "eth_cu_1000_6"; }; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts index 078d8699e16d..463c2452b9b7 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts @@ -112,7 +112,7 @@ suppress-preamble; status = "okay"; - switch0: ethernet-switch@0 { + switch0: switch0@0 { compatible = "marvell,mv88e6190"; pinctrl-0 = <&pinctrl_gpio_switch0>; pinctrl-names = "default"; @@ -123,11 +123,11 @@ interrupt-controller; #interrupt-cells = <2>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; phy-mode = "rmii"; ethernet = <&fec1>; @@ -138,27 +138,27 @@ }; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "eth_cu_100_3"; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "eth_cu_1000_4"; }; - ethernet-port@6 { + port@6 { reg = <6>; label = "eth_cu_1000_5"; }; - ethernet-port@8 { + port@8 { reg = <8>; label = "eth_cu_1000_1"; }; - ethernet-port@9 { + port@9 { reg = <9>; label = "eth_cu_1000_2"; phy-handle = <&phy9>; @@ -167,12 +167,12 @@ }; }; - mdio-external { + mdio1 { compatible = "marvell,mv88e6xxx-mdio-external"; #address-cells = <1>; #size-cells = <0>; - phy9: ethernet-phy@0 { + phy9: phy9@0 { compatible = "ethernet-phy-ieee802.3-c45"; pinctrl-0 = <&pinctrl_gpio_phy9>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts index 22c8f44390a9..f5ae0d5de315 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts @@ -137,7 +137,7 @@ suppress-preamble; status = "okay"; - switch0: ethernet-switch@0 { + switch0: switch0@0 { compatible = "marvell,mv88e6190"; pinctrl-0 = <&pinctrl_gpio_switch0>; pinctrl-names = "default"; @@ -148,11 +148,11 @@ interrupt-controller; #interrupt-cells = <2>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; phy-mode = "rmii"; ethernet = <&fec1>; @@ -163,32 +163,32 @@ }; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "eth_cu_1000_1"; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "eth_cu_1000_2"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "eth_cu_1000_3"; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "eth_cu_1000_4"; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "eth_cu_1000_5"; }; - ethernet-port@6 { + port@6 { reg = <6>; label = "eth_cu_1000_6"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 870bb380a40a..f9abef8dcc94 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -126,32 +126,32 @@ reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; - ethernet-ports { - switch0port1: ethernet-port@1 { + ports { + switch0port1: port@1 { reg = <1>; label = "lan0"; phy-handle = <&switch0phy0>; }; - switch0port2: ethernet-port@2 { + switch0port2: port@2 { reg = <2>; label = "lan1"; phy-handle = <&switch0phy1>; }; - switch0port3: ethernet-port@3 { + switch0port3: port@3 { reg = <3>; label = "lan2"; phy-handle = <&switch0phy2>; }; - switch0port4: ethernet-port@4 { + switch0port4: port@4 { reg = <4>; label = "lan3"; phy-handle = <&switch0phy3>; }; - switch0port5: ethernet-port@5 { + switch0port5: port@5 { reg = <5>; label = "wan"; phy-handle = <&extphy>; @@ -160,7 +160,7 @@ }; mdio { - switch0phy3: ethernet-phy@14 { + switch0phy3: switch0phy3@14 { reg = <0x14>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index fed2dcecb323..49cbdb55b4b3 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -145,17 +145,19 @@ }; &mdio { - switch0: ethernet-switch@1 { + switch0: switch0@1 { compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; reg = <1>; dsa,member = <0 0>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - switch0port0: ethernet-port@0 { + switch0port0: port@0 { reg = <0>; label = "cpu"; ethernet = <ð0>; @@ -166,19 +168,19 @@ }; }; - switch0port1: ethernet-port@1 { + switch0port1: port@1 { reg = <1>; label = "wan"; phy-handle = <&switch0phy0>; }; - switch0port2: ethernet-port@2 { + switch0port2: port@2 { reg = <2>; label = "lan0"; phy-handle = <&switch0phy1>; }; - switch0port3: ethernet-port@3 { + switch0port3: port@3 { reg = <3>; label = "lan1"; phy-handle = <&switch0phy2>; @@ -190,13 +192,13 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: ethernet-phy@11 { + switch0phy0: switch0phy0@11 { reg = <0x11>; }; - switch0phy1: ethernet-phy@12 { + switch0phy1: switch0phy1@12 { reg = <0x12>; }; - switch0phy2: ethernet-phy@13 { + switch0phy2: switch0phy2@13 { reg = <0x13>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index 63fbc8352161..b1b45b4fa9d4 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -152,29 +152,31 @@ }; &mdio { - switch0: ethernet-switch@1 { + switch0: switch0@1 { compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; reg = <1>; dsa,member = <0 0>; - ports: ethernet-ports { + ports: ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@0 { + port@0 { reg = <0>; label = "cpu"; ethernet = <ð0>; }; - ethernet-port@1 { + port@1 { reg = <1>; label = "wan"; phy-handle = <&switch0phy0>; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "lan0"; phy-handle = <&switch0phy1>; @@ -183,7 +185,7 @@ nvmem-cell-names = "mac-address"; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "lan1"; phy-handle = <&switch0phy2>; @@ -197,13 +199,13 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: ethernet-phy@11 { + switch0phy0: switch0phy0@11 { reg = <0x11>; }; - switch0phy1: ethernet-phy@12 { + switch0phy1: switch0phy1@12 { reg = <0x12>; }; - switch0phy2: ethernet-phy@13 { + switch0phy2: switch0phy2@13 { reg = <0x13>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index cdf1b8bdb230..9eab2bb22134 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -304,12 +304,7 @@ reg = <1>; }; - /* - * NOTE: switch nodes are enabled by U-Boot if modules are present - * DO NOT change this node name (switch0@10) even if it is not following - * conventions! Deployed U-Boot binaries are explicitly looking for - * this node in order to augment the device tree! - */ + /* switch nodes are enabled by U-Boot if modules are present */ switch0@10 { compatible = "marvell,mv88e6190"; reg = <0x10>; @@ -322,92 +317,92 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy1: ethernet-phy@1 { + switch0phy1: switch0phy1@1 { reg = <0x1>; }; - switch0phy2: ethernet-phy@2 { + switch0phy2: switch0phy2@2 { reg = <0x2>; }; - switch0phy3: ethernet-phy@3 { + switch0phy3: switch0phy3@3 { reg = <0x3>; }; - switch0phy4: ethernet-phy@4 { + switch0phy4: switch0phy4@4 { reg = <0x4>; }; - switch0phy5: ethernet-phy@5 { + switch0phy5: switch0phy5@5 { reg = <0x5>; }; - switch0phy6: ethernet-phy@6 { + switch0phy6: switch0phy6@6 { reg = <0x6>; }; - switch0phy7: ethernet-phy@7 { + switch0phy7: switch0phy7@7 { reg = <0x7>; }; - switch0phy8: ethernet-phy@8 { + switch0phy8: switch0phy8@8 { reg = <0x8>; }; }; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <0x1>; label = "lan1"; phy-handle = <&switch0phy1>; }; - ethernet-port@2 { + port@2 { reg = <0x2>; label = "lan2"; phy-handle = <&switch0phy2>; }; - ethernet-port@3 { + port@3 { reg = <0x3>; label = "lan3"; phy-handle = <&switch0phy3>; }; - ethernet-port@4 { + port@4 { reg = <0x4>; label = "lan4"; phy-handle = <&switch0phy4>; }; - ethernet-port@5 { + port@5 { reg = <0x5>; label = "lan5"; phy-handle = <&switch0phy5>; }; - ethernet-port@6 { + port@6 { reg = <0x6>; label = "lan6"; phy-handle = <&switch0phy6>; }; - ethernet-port@7 { + port@7 { reg = <0x7>; label = "lan7"; phy-handle = <&switch0phy7>; }; - ethernet-port@8 { + port@8 { reg = <0x8>; label = "lan8"; phy-handle = <&switch0phy8>; }; - ethernet-port@9 { + port@9 { reg = <0x9>; label = "cpu"; ethernet = <ð1>; @@ -415,7 +410,7 @@ managed = "in-band-status"; }; - switch0port10: ethernet-port@a { + switch0port10: port@a { reg = <0xa>; label = "dsa"; phy-mode = "2500base-x"; @@ -435,7 +430,7 @@ }; }; - ethernet-switch@2 { + switch0@2 { compatible = "marvell,mv88e6085"; reg = <0x2>; dsa,member = <0 0>; @@ -447,52 +442,52 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy1_topaz: ethernet-phy@11 { + switch0phy1_topaz: switch0phy1@11 { reg = <0x11>; }; - switch0phy2_topaz: ethernet-phy@12 { + switch0phy2_topaz: switch0phy2@12 { reg = <0x12>; }; - switch0phy3_topaz: ethernet-phy@13 { + switch0phy3_topaz: switch0phy3@13 { reg = <0x13>; }; - switch0phy4_topaz: ethernet-phy@14 { + switch0phy4_topaz: switch0phy4@14 { reg = <0x14>; }; }; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <0x1>; label = "lan1"; phy-handle = <&switch0phy1_topaz>; }; - ethernet-port@2 { + port@2 { reg = <0x2>; label = "lan2"; phy-handle = <&switch0phy2_topaz>; }; - ethernet-port@3 { + port@3 { reg = <0x3>; label = "lan3"; phy-handle = <&switch0phy3_topaz>; }; - ethernet-port@4 { + port@4 { reg = <0x4>; label = "lan4"; phy-handle = <&switch0phy4_topaz>; }; - ethernet-port@5 { + port@5 { reg = <0x5>; label = "cpu"; phy-mode = "2500base-x"; @@ -502,7 +497,7 @@ }; }; - ethernet-switch@11 { + switch1@11 { compatible = "marvell,mv88e6190"; reg = <0x11>; dsa,member = <0 1>; @@ -514,92 +509,92 @@ #address-cells = <1>; #size-cells = <0>; - switch1phy1: ethernet-phy@1 { + switch1phy1: switch1phy1@1 { reg = <0x1>; }; - switch1phy2: ethernet-phy@2 { + switch1phy2: switch1phy2@2 { reg = <0x2>; }; - switch1phy3: ethernet-phy@3 { + switch1phy3: switch1phy3@3 { reg = <0x3>; }; - switch1phy4: ethernet-phy@4 { + switch1phy4: switch1phy4@4 { reg = <0x4>; }; - switch1phy5: ethernet-phy@5 { + switch1phy5: switch1phy5@5 { reg = <0x5>; }; - switch1phy6: ethernet-phy@6 { + switch1phy6: switch1phy6@6 { reg = <0x6>; }; - switch1phy7: ethernet-phy@7 { + switch1phy7: switch1phy7@7 { reg = <0x7>; }; - switch1phy8: ethernet-phy@8 { + switch1phy8: switch1phy8@8 { reg = <0x8>; }; }; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <0x1>; label = "lan9"; phy-handle = <&switch1phy1>; }; - ethernet-port@2 { + port@2 { reg = <0x2>; label = "lan10"; phy-handle = <&switch1phy2>; }; - ethernet-port@3 { + port@3 { reg = <0x3>; label = "lan11"; phy-handle = <&switch1phy3>; }; - ethernet-port@4 { + port@4 { reg = <0x4>; label = "lan12"; phy-handle = <&switch1phy4>; }; - ethernet-port@5 { + port@5 { reg = <0x5>; label = "lan13"; phy-handle = <&switch1phy5>; }; - ethernet-port@6 { + port@6 { reg = <0x6>; label = "lan14"; phy-handle = <&switch1phy6>; }; - ethernet-port@7 { + port@7 { reg = <0x7>; label = "lan15"; phy-handle = <&switch1phy7>; }; - ethernet-port@8 { + port@8 { reg = <0x8>; label = "lan16"; phy-handle = <&switch1phy8>; }; - switch1port9: ethernet-port@9 { + switch1port9: port@9 { reg = <0x9>; label = "dsa"; phy-mode = "2500base-x"; @@ -607,7 +602,7 @@ link = <&switch0port10>; }; - switch1port10: ethernet-port@a { + switch1port10: port@a { reg = <0xa>; label = "dsa"; phy-mode = "2500base-x"; @@ -627,7 +622,7 @@ }; }; - ethernet-switch@2 { + switch1@2 { compatible = "marvell,mv88e6085"; reg = <0x2>; dsa,member = <0 1>; @@ -639,52 +634,52 @@ #address-cells = <1>; #size-cells = <0>; - switch1phy1_topaz: ethernet-phy@11 { + switch1phy1_topaz: switch1phy1@11 { reg = <0x11>; }; - switch1phy2_topaz: ethernet-phy@12 { + switch1phy2_topaz: switch1phy2@12 { reg = <0x12>; }; - switch1phy3_topaz: ethernet-phy@13 { + switch1phy3_topaz: switch1phy3@13 { reg = <0x13>; }; - switch1phy4_topaz: ethernet-phy@14 { + switch1phy4_topaz: switch1phy4@14 { reg = <0x14>; }; }; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <0x1>; label = "lan9"; phy-handle = <&switch1phy1_topaz>; }; - ethernet-port@2 { + port@2 { reg = <0x2>; label = "lan10"; phy-handle = <&switch1phy2_topaz>; }; - ethernet-port@3 { + port@3 { reg = <0x3>; label = "lan11"; phy-handle = <&switch1phy3_topaz>; }; - ethernet-port@4 { + port@4 { reg = <0x4>; label = "lan12"; phy-handle = <&switch1phy4_topaz>; }; - ethernet-port@5 { + port@5 { reg = <0x5>; label = "dsa"; phy-mode = "2500base-x"; @@ -694,7 +689,7 @@ }; }; - ethernet-switch@12 { + switch2@12 { compatible = "marvell,mv88e6190"; reg = <0x12>; dsa,member = <0 2>; @@ -706,92 +701,92 @@ #address-cells = <1>; #size-cells = <0>; - switch2phy1: ethernet-phy@1 { + switch2phy1: switch2phy1@1 { reg = <0x1>; }; - switch2phy2: ethernet-phy@2 { + switch2phy2: switch2phy2@2 { reg = <0x2>; }; - switch2phy3: ethernet-phy@3 { + switch2phy3: switch2phy3@3 { reg = <0x3>; }; - switch2phy4: ethernet-phy@4 { + switch2phy4: switch2phy4@4 { reg = <0x4>; }; - switch2phy5: ethernet-phy@5 { + switch2phy5: switch2phy5@5 { reg = <0x5>; }; - switch2phy6: ethernet-phy@6 { + switch2phy6: switch2phy6@6 { reg = <0x6>; }; - switch2phy7: ethernet-phy@7 { + switch2phy7: switch2phy7@7 { reg = <0x7>; }; - switch2phy8: ethernet-phy@8 { + switch2phy8: switch2phy8@8 { reg = <0x8>; }; }; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <0x1>; label = "lan17"; phy-handle = <&switch2phy1>; }; - ethernet-port@2 { + port@2 { reg = <0x2>; label = "lan18"; phy-handle = <&switch2phy2>; }; - ethernet-port@3 { + port@3 { reg = <0x3>; label = "lan19"; phy-handle = <&switch2phy3>; }; - ethernet-port@4 { + port@4 { reg = <0x4>; label = "lan20"; phy-handle = <&switch2phy4>; }; - ethernet-port@5 { + port@5 { reg = <0x5>; label = "lan21"; phy-handle = <&switch2phy5>; }; - ethernet-port@6 { + port@6 { reg = <0x6>; label = "lan22"; phy-handle = <&switch2phy6>; }; - ethernet-port@7 { + port@7 { reg = <0x7>; label = "lan23"; phy-handle = <&switch2phy7>; }; - ethernet-port@8 { + port@8 { reg = <0x8>; label = "lan24"; phy-handle = <&switch2phy8>; }; - switch2port9: ethernet-port@9 { + switch2port9: port@9 { reg = <0x9>; label = "dsa"; phy-mode = "2500base-x"; @@ -810,7 +805,7 @@ }; }; - ethernet-switch@2 { + switch2@2 { compatible = "marvell,mv88e6085"; reg = <0x2>; dsa,member = <0 2>; @@ -822,52 +817,52 @@ #address-cells = <1>; #size-cells = <0>; - switch2phy1_topaz: ethernet-phy@11 { + switch2phy1_topaz: switch2phy1@11 { reg = <0x11>; }; - switch2phy2_topaz: ethernet-phy@12 { + switch2phy2_topaz: switch2phy2@12 { reg = <0x12>; }; - switch2phy3_topaz: ethernet-phy@13 { + switch2phy3_topaz: switch2phy3@13 { reg = <0x13>; }; - switch2phy4_topaz: ethernet-phy@14 { + switch2phy4_topaz: switch2phy4@14 { reg = <0x14>; }; }; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <0x1>; label = "lan17"; phy-handle = <&switch2phy1_topaz>; }; - ethernet-port@2 { + port@2 { reg = <0x2>; label = "lan18"; phy-handle = <&switch2phy2_topaz>; }; - ethernet-port@3 { + port@3 { reg = <0x3>; label = "lan19"; phy-handle = <&switch2phy3_topaz>; }; - ethernet-port@4 { + port@4 { reg = <0x4>; label = "lan20"; phy-handle = <&switch2phy4_topaz>; }; - ethernet-port@5 { + port@5 { reg = <0x5>; label = "dsa"; phy-mode = "2500base-x"; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts index 40b7ee7ead72..48202810bf78 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -301,8 +301,10 @@ }; /* 88E6141 Topaz switch */ - switch: ethernet-switch@3 { + switch: switch@3 { compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; reg = <3>; pinctrl-names = "default"; @@ -312,35 +314,35 @@ interrupt-parent = <&cp0_gpio1>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - swport1: ethernet-port@1 { + swport1: port@1 { reg = <1>; label = "lan0"; phy-handle = <&swphy1>; }; - swport2: ethernet-port@2 { + swport2: port@2 { reg = <2>; label = "lan1"; phy-handle = <&swphy2>; }; - swport3: ethernet-port@3 { + swport3: port@3 { reg = <3>; label = "lan2"; phy-handle = <&swphy3>; }; - swport4: ethernet-port@4 { + swport4: port@4 { reg = <4>; label = "lan3"; phy-handle = <&swphy4>; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "cpu"; ethernet = <&cp0_eth1>; @@ -353,19 +355,19 @@ #address-cells = <1>; #size-cells = <0>; - swphy1: ethernet-phy@17 { + swphy1: swphy1@17 { reg = <17>; }; - swphy2: ethernet-phy@18 { + swphy2: swphy2@18 { reg = <18>; }; - swphy3: ethernet-phy@19 { + swphy3: swphy3@19 { reg = <19>; }; - swphy4: ethernet-phy@20 { + swphy4: swphy4@20 { reg = <20>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 67892f0d2863..4125202028c8 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -497,42 +497,42 @@ reset-deassert-us = <10000>; }; - switch0: ethernet-switch@4 { + switch0: switch0@4 { compatible = "marvell,mv88e6085"; reg = <4>; pinctrl-names = "default"; pinctrl-0 = <&cp1_switch_reset_pins>; reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <1>; label = "lan2"; phy-handle = <&switch0phy0>; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "lan1"; phy-handle = <&switch0phy1>; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "lan4"; phy-handle = <&switch0phy2>; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "lan3"; phy-handle = <&switch0phy3>; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "cpu"; ethernet = <&cp1_eth2>; @@ -545,19 +545,19 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: ethernet-phy@11 { + switch0phy0: switch0phy0@11 { reg = <0x11>; }; - switch0phy1: ethernet-phy@12 { + switch0phy1: switch0phy1@12 { reg = <0x12>; }; - switch0phy2: ethernet-phy@13 { + switch0phy2: switch0phy2@13 { reg = <0x13>; }; - switch0phy3: ethernet-phy@14 { + switch0phy3: switch0phy3@14 { reg = <0x14>; }; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 7538ed56053b..32cfb3e2efc3 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -207,9 +207,11 @@ reg = <0>; }; - switch6: ethernet-switch@6 { + switch6: switch0@6 { /* Actual device is MV88E6393X */ compatible = "marvell,mv88e6190"; + #address-cells = <1>; + #size-cells = <0>; reg = <6>; interrupt-parent = <&cp0_gpio1>; interrupts = <28 IRQ_TYPE_LEVEL_LOW>; @@ -218,59 +220,59 @@ dsa,member = <0 0>; - ethernet-ports { + ports { #address-cells = <1>; #size-cells = <0>; - ethernet-port@1 { + port@1 { reg = <1>; label = "p1"; phy-handle = <&switch0phy1>; }; - ethernet-port@2 { + port@2 { reg = <2>; label = "p2"; phy-handle = <&switch0phy2>; }; - ethernet-port@3 { + port@3 { reg = <3>; label = "p3"; phy-handle = <&switch0phy3>; }; - ethernet-port@4 { + port@4 { reg = <4>; label = "p4"; phy-handle = <&switch0phy4>; }; - ethernet-port@5 { + port@5 { reg = <5>; label = "p5"; phy-handle = <&switch0phy5>; }; - ethernet-port@6 { + port@6 { reg = <6>; label = "p6"; phy-handle = <&switch0phy6>; }; - ethernet-port@7 { + port@7 { reg = <7>; label = "p7"; phy-handle = <&switch0phy7>; }; - ethernet-port@8 { + port@8 { reg = <8>; label = "p8"; phy-handle = <&switch0phy8>; }; - ethernet-port@9 { + port@9 { reg = <9>; label = "p9"; phy-mode = "10gbase-r"; @@ -278,7 +280,7 @@ managed = "in-band-status"; }; - ethernet-port@a { + port@a { reg = <10>; ethernet = <&cp0_eth0>; phy-mode = "10gbase-r"; @@ -291,35 +293,35 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy1: ethernet-phy@1 { + switch0phy1: switch0phy1@1 { reg = <0x1>; }; - switch0phy2: ethernet-phy@2 { + switch0phy2: switch0phy2@2 { reg = <0x2>; }; - switch0phy3: ethernet-phy@3 { + switch0phy3: switch0phy3@3 { reg = <0x3>; }; - switch0phy4: ethernet-phy@4 { + switch0phy4: switch0phy4@4 { reg = <0x4>; }; - switch0phy5: ethernet-phy@5 { + switch0phy5: switch0phy5@5 { reg = <0x5>; }; - switch0phy6: ethernet-phy@6 { + switch0phy6: switch0phy6@6 { reg = <0x6>; }; - switch0phy7: ethernet-phy@7 { + switch0phy7: switch0phy7@7 { reg = <0x7>; }; - switch0phy8: ethernet-phy@8 { + switch0phy8: switch0phy8@8 { reg = <0x8>; }; }; |