diff options
Diffstat (limited to 'drivers/gpu/drm/panel')
| -rw-r--r-- | drivers/gpu/drm/panel/Kconfig | 31 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/Makefile | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-ebbg-ft8719.c | 67 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-edp.c | 23 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-himax-hx83102.c | 380 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-ilitek-ili9882t.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-raydium-rm67200.c | 499 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c | 91 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c | 59 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-simple.c | 64 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-sony-td4353-jdi.c | 107 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-summit.c | 132 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-visionox-r66451.c | 181 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-visionox-rm692e5.c | 442 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c | 178 |
16 files changed, 1820 insertions, 443 deletions
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index d7469c565d1d..e059b06e0239 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -573,6 +573,16 @@ config DRM_PANEL_RAYDIUM_RM67191 Say Y here if you want to enable support for Raydium RM67191 FHD (1080x1920) DSI panel. +config DRM_PANEL_RAYDIUM_RM67200 + tristate "Raydium RM67200-based DSI panel" + depends on OF + depends on DRM_MIPI_DSI + help + Say Y here if you want to enable support for Raydium RM67200-based + DSI video mode panels. This panel controller can be found in the + Wanchanglong W552793BAA panel found on the Rockchip RK3588 EVB1 + evaluation boards. + config DRM_PANEL_RAYDIUM_RM68200 tristate "Raydium RM68200 720x1280 DSI video mode panel" depends on OF @@ -925,6 +935,15 @@ config DRM_PANEL_SIMPLE that it can be automatically turned off when the panel goes into a low power state. +config DRM_PANEL_SUMMIT + tristate "Apple Summit display panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y if you want to enable support for the "Summit" display panel + used as a touchbar on certain Apple laptops. + config DRM_PANEL_SYNAPTICS_R63353 tristate "Synaptics R63353-based panels" depends on OF @@ -996,6 +1015,18 @@ config DRM_PANEL_VISIONOX_RM69299 Say Y here if you want to enable support for Visionox RM69299 DSI Video Mode panel. +config DRM_PANEL_VISIONOX_RM692E5 + tristate "Visionox RM692E5" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select DRM_DISPLAY_DSC_HELPER + select DRM_DISPLAY_HELPER + help + Say Y here if you want to enable support for Visionox RM692E5 amoled + display panels, such as the one found in the Nothing Phone (1) + smartphone. + config DRM_PANEL_VISIONOX_VTDR6130 tristate "Visionox VTDR6130" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 7dcf72646cac..1bb8ae46b59b 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS) += panel-osd-osd101t2587-53ts.o obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o +obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67200) += panel-raydium-rm67200.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM692E5) += panel-raydium-rm692e5.o obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM69380) += panel-raydium-rm69380.o @@ -89,6 +90,7 @@ obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o +obj-$(CONFIG_DRM_PANEL_SUMMIT) += panel-summit.o obj-$(CONFIG_DRM_PANEL_SYNAPTICS_R63353) += panel-synaptics-r63353.o obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o obj-$(CONFIG_DRM_PANEL_SONY_TD4353_JDI) += panel-sony-td4353-jdi.o @@ -100,6 +102,7 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o +obj-$(CONFIG_DRM_PANEL_VISIONOX_RM692E5) += panel-visionox-rm692e5.o obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o diff --git a/drivers/gpu/drm/panel/panel-ebbg-ft8719.c b/drivers/gpu/drm/panel/panel-ebbg-ft8719.c index e85d63a176d0..0bfed0ec0bbc 100644 --- a/drivers/gpu/drm/panel/panel-ebbg-ft8719.c +++ b/drivers/gpu/drm/panel/panel-ebbg-ft8719.c @@ -57,65 +57,39 @@ static void ebbg_ft8719_reset(struct ebbg_ft8719 *ctx) static int ebbg_ft8719_on(struct ebbg_ft8719 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_brightness(dsi, 0x00ff); - if (ret < 0) { - dev_err(dev, "Failed to set display brightness: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 90); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(90); - - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display on: %d\n", ret); - return ret; - } - - return 0; + return dsi_ctx.accum_err; } static int ebbg_ft8719_off(struct ebbg_ft8719 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - usleep_range(10000, 11000); - - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(90); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 10000, 11000); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 90); - return 0; + return dsi_ctx.accum_err; } static int ebbg_ft8719_prepare(struct drm_panel *panel) { struct ebbg_ft8719 *ctx = to_ebbg_ft8719(panel); - struct device *dev = &ctx->dsi->dev; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); @@ -126,7 +100,6 @@ static int ebbg_ft8719_prepare(struct drm_panel *panel) ret = ebbg_ft8719_on(ctx); if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); gpiod_set_value_cansleep(ctx->reset_gpio, 1); return ret; } @@ -137,18 +110,10 @@ static int ebbg_ft8719_prepare(struct drm_panel *panel) static int ebbg_ft8719_unprepare(struct drm_panel *panel) { struct ebbg_ft8719 *ctx = to_ebbg_ft8719(panel); - struct device *dev = &ctx->dsi->dev; - int ret; - - ret = ebbg_ft8719_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + ebbg_ft8719_off(ctx); gpiod_set_value_cansleep(ctx->reset_gpio, 1); - - ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - if (ret) - dev_err(panel->dev, "Failed to disable regulators: %d\n", ret); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); return 0; } diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c index f8511fe5fb0d..52028c8f8988 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c @@ -1808,6 +1808,20 @@ static const struct panel_delay delay_200_150_e50 = { .enable = 50, }; +static const struct panel_delay delay_200_500_e250 = { + .hpd_absent = 200, + .unprepare = 500, + .enable = 250, +}; + +static const struct panel_delay delay_50_500_e200_d200_po2e335 = { + .hpd_absent = 50, + .unprepare = 500, + .enable = 200, + .disable = 200, + .powered_on_to_enable = 335, +}; + #define EDP_PANEL_ENTRY(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _delay, _name) \ { \ .ident = { \ @@ -1862,6 +1876,7 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('A', 'U', 'O', 0x73aa, &delay_200_500_e50, "B116XTN02.3"), EDP_PANEL_ENTRY('A', 'U', 'O', 0x8594, &delay_200_500_e50, "B133UAN01.0"), EDP_PANEL_ENTRY('A', 'U', 'O', 0xa199, &delay_200_500_e50, "B116XAN06.1"), + EDP_PANEL_ENTRY('A', 'U', 'O', 0xa7b3, &delay_200_500_e50, "B140UAN04.4"), EDP_PANEL_ENTRY('A', 'U', 'O', 0xc4b4, &delay_200_500_e50, "B116XAT04.1"), EDP_PANEL_ENTRY('A', 'U', 'O', 0xd497, &delay_200_500_e50, "B120XAN01.0"), EDP_PANEL_ENTRY('A', 'U', 'O', 0xf390, &delay_200_500_e50, "B140XTN07.7"), @@ -1914,6 +1929,7 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a5d, &delay_200_500_e50, "NV116WHM-N45"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ac5, &delay_200_500_e50, "NV116WHM-N4C"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ae8, &delay_200_500_e50_p2e80, "NV140WUM-N41"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b09, &delay_200_500_e50_po2e200, "NV140FHM-NZ"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b34, &delay_200_500_e80, "NV122WUM-N41"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b43, &delay_200_500_e200, "NV140FHM-T09"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b56, &delay_200_500_e80, "NT140FHM-N47"), @@ -1951,9 +1967,14 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('C', 'M', 'N', 0x14e5, &delay_200_500_e80_d50, "N140HGA-EA1"), EDP_PANEL_ENTRY('C', 'S', 'O', 0x1200, &delay_200_500_e50_p2e200, "MNC207QS1-1"), + EDP_PANEL_ENTRY('C', 'S', 'O', 0x1413, &delay_200_500_e50_p2e200, "MNE007JA1-2"), EDP_PANEL_ENTRY('C', 'S', 'W', 0x1100, &delay_200_500_e80_d50, "MNB601LS1-1"), + EDP_PANEL_ENTRY('C', 'S', 'W', 0x1103, &delay_200_500_e80_d50, "MNB601LS1-3"), EDP_PANEL_ENTRY('C', 'S', 'W', 0x1104, &delay_200_500_e50, "MNB601LS1-4"), + EDP_PANEL_ENTRY('C', 'S', 'W', 0x1448, &delay_200_500_e50, "MNE007QS3-7"), + + EDP_PANEL_ENTRY('E', 'T', 'C', 0x0000, &delay_50_500_e200_d200_po2e335, "LP079QX1-SP0V"), EDP_PANEL_ENTRY('H', 'K', 'C', 0x2d51, &delay_200_500_e200, "Unknown"), EDP_PANEL_ENTRY('H', 'K', 'C', 0x2d5b, &delay_200_500_e200, "MB116AN01"), @@ -1993,6 +2014,8 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('S', 'H', 'P', 0x154c, &delay_200_500_p2e100, "LQ116M1JW10"), EDP_PANEL_ENTRY('S', 'H', 'P', 0x1593, &delay_200_500_p2e100, "LQ134N1"), + EDP_PANEL_ENTRY('S', 'T', 'A', 0x0004, &delay_200_500_e200, "116KHD024006"), + EDP_PANEL_ENTRY('S', 'T', 'A', 0x0009, &delay_200_500_e250, "116QHD024002"), EDP_PANEL_ENTRY('S', 'T', 'A', 0x0100, &delay_100_500_e200, "2081116HHD028001-51D"), { /* sentinal */ } diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/panel/panel-himax-hx83102.c index 3644a7544b93..66abfc44e424 100644 --- a/drivers/gpu/drm/panel/panel-himax-hx83102.c +++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c @@ -24,6 +24,8 @@ #define HX83102_SETPOWER 0xb1 #define HX83102_SETDISP 0xb2 #define HX83102_SETCYC 0xb4 +#define HX83102_UNKNOWN_B6 0xb6 +#define HX83102_UNKNOWN_B8 0xb8 #define HX83102_SETEXTC 0xb9 #define HX83102_SETMIPI 0xba #define HX83102_SETVDC 0xbc @@ -43,6 +45,7 @@ #define HX83102_SETGIP1 0xd5 #define HX83102_SETGIP2 0xd6 #define HX83102_SETGIP3 0xd8 +#define HX83102_UNKNOWN_D9 0xd9 #define HX83102_SETGMA 0xe0 #define HX83102_UNKNOWN_E1 0xe1 #define HX83102_SETTP1 0xe7 @@ -291,6 +294,103 @@ static int boe_nv110wum_init(struct hx83102 *ctx) return dsi_ctx.accum_err; }; +static int csot_pna957qt1_1_init(struct hx83102 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + msleep(60); + + hx83102_enable_extended_cmds(&dsi_ctx, true); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd2); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb3, 0xb3, 0x31, 0xf1, 0x33, + 0xe0, 0x54, 0x36, 0x36, 0x3a, 0x3a, 0x32, 0x8b, 0x11, 0xe5, + 0x98); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x8b, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x2c, + 0x80, 0x3c, 0x9f, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x41, 0x41, 0x41, 0x41, 0x64, 0x64, + 0x40, 0x84, 0x64, 0x84, 0x01, 0x9d, 0x01, 0x02, 0x01, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4, 0x80, 0x9c, 0x36, 0x00, + 0x0d, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x32, 0x32, 0x22, 0x11, 0x22, 0xa0, + 0x31, 0x08, 0xf5, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, + 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 0x04, 0x2c, + 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x40, 0x04, + 0x08, 0x04, 0x08, 0x37, 0x07, 0x44, 0x37, 0x2b, 0x2b, 0x03, + 0x03, 0x32, 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, + 0x29, 0x32, 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, + 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, + 0x18, 0x18, 0x25, 0x24, 0x25, 0x24, 0x1f, 0x1f, 0x1f, 0x1f, + 0x1e, 0x1e, 0x1e, 0x1e, 0x20, 0x20, 0x20, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x0a, 0x0e, 0x1a, 0x21, 0x28, 0x46, + 0x5c, 0x61, 0x63, 0x5e, 0x78, 0x7d, 0x80, 0x8e, 0x89, 0x90, + 0x98, 0xaa, 0xa8, 0x52, 0x59, 0x60, 0x6f, 0x06, 0x0a, 0x16, + 0x1d, 0x24, 0x46, 0x5c, 0x61, 0x6b, 0x66, 0x7c, 0x7d, 0x80, + 0x8e, 0x89, 0x90, 0x98, 0xaa, 0xa8, 0x52, 0x59, 0x60, 0x6f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xe0, 0x10, 0x10, 0x0d, 0x1e, 0x9d, + 0x02, 0x52, 0x9d, 0x14, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x64); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x05, 0x15, 0x55, 0x45, + 0x55, 0x50, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x24, 0x01, 0x7e, 0x0f, + 0x7c, 0x10, 0xa0, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x7b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0, + 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, + 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, + 0x20, 0x9d, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x66, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x0f, 0x2a, 0xaa, 0x8a, + 0xaa, 0xf0, 0x0f, 0x2a, 0xaa, 0x8a, 0xaa, 0xf0, 0x0a, 0x2a, + 0xaa, 0x8a, 0xaa, 0xa0, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + hx83102_enable_extended_cmds(&dsi_ctx, false); + + mipi_dsi_msleep(&dsi_ctx, 60); + + return dsi_ctx.accum_err; +}; + static int ivo_t109nw41_init(struct hx83102 *ctx) { struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; @@ -396,6 +496,211 @@ static int ivo_t109nw41_init(struct hx83102 *ctx) return dsi_ctx.accum_err; }; +static int kingdisplay_kd110n11_51ie_init(struct hx83102 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + msleep(50); + + hx83102_enable_extended_cmds(&dsi_ctx, true); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb3, 0xb3, 0x31, 0xf1, + 0x33, 0xe0, 0x54, 0x36, 0x36, 0x3a, 0x3a, 0x32, 0x8b, + 0x11, 0xe5, 0x98); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x8b, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x2c, + 0x80, 0x3c, 0x9f, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, + 0x40, 0x84, 0x64, 0x84, 0x01, 0x9d, 0x01, 0x02, 0x01, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4, 0x80, 0x9c, 0x36, 0x00, + 0x0d, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x32, 0x32, 0x22, 0x11, 0x22, 0xa0, + 0x31, 0x08, 0xf5, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, + 0x0f, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, + 0x04, 0x2c, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x40, 0x04, + 0x08, 0x04, 0x08, 0x37, 0x07, 0x44, 0x37, 0x2b, 0x2b, 0x03, + 0x03, 0x32, 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, + 0x29, 0x32, 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, + 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, + 0x18, 0x18, 0x25, 0x24, 0x25, 0x24, 0x1f, 0x1f, 0x1f, 0x1f, + 0x1e, 0x1e, 0x1e, 0x1e, 0x20, 0x20, 0x20, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xe0, 0x10, 0x10, 0x0d, 0x1e, 0x9d, + 0x02, 0x52, 0x9d, 0x14, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x64); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x05, 0x15, 0x55, 0x45, + 0x55, 0x50, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x24, 0x01, 0x7e, 0x0f, + 0x7c, 0x10, 0xa0, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x7b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0, + 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, + 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, + 0x20, 0x9d, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x66, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x0f, 0x2a, 0xaa, 0x8a, + 0xaa, 0xf0, 0x0f, 0x2a, 0xaa, 0x8a, 0xaa, 0xf0, 0x0a, 0x2a, + 0xaa, 0x8a, 0xaa, 0xa0, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + hx83102_enable_extended_cmds(&dsi_ctx, false); + + return dsi_ctx.accum_err; +} + +static int starry_2082109qfh040022_50e_init(struct hx83102 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + msleep(50); + + hx83102_enable_extended_cmds(&dsi_ctx, true); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb5, 0xb5, 0x31, 0xf1, 0x33, + 0xc3, 0x57, 0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11, 0x65, + 0x00, 0x88, 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x3c, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x22, + 0x70, 0x3c, 0xa1, 0x22, 0x00, 0x00, 0x00, 0x88, 0xf4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x14, 0x16, 0x14, 0x50, 0x14, 0x50, + 0x0d, 0x6a, 0x0d, 0x6a, 0x01, 0x9e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x34, 0x34, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B8, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x38, 0x38, 0x22, 0x11, 0x33, 0xa0, + 0x61, 0x08, 0xf5, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x30, 0xd4, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, + 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06, 0x00, 0x02, 0x04, + 0x2c, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x3b, 0x03, 0x73, 0x3b, 0x21, 0x21, 0x03, + 0x03, 0x98, 0x10, 0x1d, 0x00, 0x1d, 0x32, 0x17, 0xa1, 0x07, + 0xa1, 0x43, 0x17, 0xa6, 0x07, 0xa6, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x2a, 0x2b, 0x1f, 0x1f, + 0x1e, 0x1e, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, + 0x0a, 0x0b, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x02, 0xaa, 0xea, 0xaa, 0xaa, 0x00, + 0x02, 0xaa, 0xea, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x2a, 0x32, 0x9f, + 0x01, 0x5a, 0x91, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, + 0x05, 0x02, 0x02, 0x10, 0x33, 0x02, 0x04, 0x18, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x3d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x00, 0x80, 0x80, 0x0c, + 0xa1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x03, 0xff, 0xff, 0xff, 0xff, 0x00, + 0x03, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x2d, 0x01, 0x7f, 0x0f, + 0x7c, 0x10, 0xa0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x02, 0x00, 0x00, 0x10, 0x58); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x0a, 0x0a, 0x05, 0x03, 0x0a, + 0x0a, 0x01, 0x03, 0x01, 0x01, 0x05, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x03, 0x1f, 0xe0, 0x11, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xab, 0xff, 0xff, 0xff, 0xff, 0xa0, + 0xab, 0xff, 0xff, 0xff, 0xff, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x81, 0x02, 0x40, 0x00, + 0x20, 0x9e, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xab, 0xea, 0xaa, 0xaa, 0xa0, + 0xaa, 0xab, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xbf, 0xff, 0xff, + 0xfe, 0xa0, 0xaa, 0xbf, 0xff, 0xff, 0xfe, 0xa0, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + hx83102_enable_extended_cmds(&dsi_ctx, false); + + mipi_dsi_msleep(&dsi_ctx, 110); + + return dsi_ctx.accum_err; +} + static const struct drm_display_mode starry_mode = { .clock = 162680, .hdisplay = 1200, @@ -440,6 +745,28 @@ static const struct hx83102_panel_desc boe_nv110wum_desc = { .init = boe_nv110wum_init, }; +static const struct drm_display_mode csot_pna957qt1_1_default_mode = { + .clock = 177958, + .hdisplay = 1200, + .hsync_start = 1200 + 124, + .hsync_end = 1200 + 124 + 80, + .htotal = 1200 + 124 + 80 + 40, + .vdisplay = 1920, + .vsync_start = 1920 + 88, + .vsync_end = 1920 + 88 + 8, + .vtotal = 1920 + 88 + 8 + 38, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct hx83102_panel_desc csot_pna957qt1_1_desc = { + .modes = &csot_pna957qt1_1_default_mode, + .size = { + .width_mm = 147, + .height_mm = 235, + }, + .init = csot_pna957qt1_1_init, +}; + static const struct drm_display_mode ivo_t109nw41_default_mode = { .clock = 167700, .hdisplay = 1200, @@ -462,6 +789,50 @@ static const struct hx83102_panel_desc ivo_t109nw41_desc = { .init = ivo_t109nw41_init, }; +static const struct drm_display_mode kingdisplay_kd110n11_51ie_default_mode = { + .clock = 182750, + .hdisplay = 1200, + .hsync_start = 1200 + 124, + .hsync_end = 1200 + 124 + 80, + .htotal = 1200 + 124 + 80 + 80, + .vdisplay = 1920, + .vsync_start = 1920 + 88, + .vsync_end = 1920 + 88 + 8, + .vtotal = 1920 + 88 + 8 + 38, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct hx83102_panel_desc kingdisplay_kd110n11_51ie_desc = { + .modes = &kingdisplay_kd110n11_51ie_default_mode, + .size = { + .width_mm = 147, + .height_mm = 235, + }, + .init = kingdisplay_kd110n11_51ie_init, +}; + +static const struct drm_display_mode starry_2082109qfh040022_50e_default_mode = { + .clock = 192050, + .hdisplay = 1200, + .hsync_start = 1200 + 160, + .hsync_end = 1200 + 160 + 66, + .htotal = 1200 + 160 + 66 + 120, + .vdisplay = 1920, + .vsync_start = 1920 + 115, + .vsync_end = 1920 + 115 + 8, + .vtotal = 1920 + 115 + 8 + 28, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct hx83102_panel_desc starry_2082109qfh040022_50e_desc = { + .modes = &starry_2082109qfh040022_50e_default_mode, + .size = { + .width_mm = 147, + .height_mm = 235, + }, + .init = starry_2082109qfh040022_50e_init, +}; + static int hx83102_enable(struct drm_panel *panel) { msleep(130); @@ -683,9 +1054,18 @@ static const struct of_device_id hx83102_of_match[] = { { .compatible = "boe,nv110wum-l60", .data = &boe_nv110wum_desc }, + { .compatible = "csot,pna957qt1-1", + .data = &csot_pna957qt1_1_desc + }, { .compatible = "ivo,t109nw41", .data = &ivo_t109nw41_desc }, + { .compatible = "kingdisplay,kd110n11-51ie", + .data = &kingdisplay_kd110n11_51ie_desc + }, + { .compatible = "starry,2082109qfh040022-50e", + .data = &starry_2082109qfh040022_50e_desc + }, { .compatible = "starry,himax83102-j02", .data = &starry_desc }, diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9882t.c b/drivers/gpu/drm/panel/panel-ilitek-ili9882t.c index 266a087fe14c..3c24a63b6be8 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9882t.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9882t.c @@ -607,7 +607,7 @@ static int ili9882t_add(struct ili9882t *ili) ili->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); if (IS_ERR(ili->enable_gpio)) { - dev_err(dev, "cannot get reset-gpios %ld\n", + dev_err(dev, "cannot get enable-gpios %ld\n", PTR_ERR(ili->enable_gpio)); return PTR_ERR(ili->enable_gpio); } diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index 7d68a8acfe2e..eb0f8373258c 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -129,11 +129,11 @@ static int jadard_unprepare(struct drm_panel *panel) { struct jadard *jadard = panel_to_jadard(panel); - gpiod_set_value(jadard->reset, 1); + gpiod_set_value(jadard->reset, 0); msleep(120); if (jadard->desc->reset_before_power_off_vcioo) { - gpiod_set_value(jadard->reset, 0); + gpiod_set_value(jadard->reset, 1); usleep_range(1000, 2000); } diff --git a/drivers/gpu/drm/panel/panel-raydium-rm67200.c b/drivers/gpu/drm/panel/panel-raydium-rm67200.c new file mode 100644 index 000000000000..64b685dc11f6 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-raydium-rm67200.c @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2024 Collabora + +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/property.h> +#include <linux/regulator/consumer.h> + +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> + +struct raydium_rm67200_panel_info { + struct drm_display_mode mode; + const struct regulator_bulk_data *regulators; + int num_regulators; + void (*panel_setup)(struct mipi_dsi_multi_context *ctx); +}; + +struct raydium_rm67200 { + struct drm_panel panel; + const struct raydium_rm67200_panel_info *panel_info; + struct mipi_dsi_device *dsi; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data *supplies; + int num_supplies; +}; + +static inline struct raydium_rm67200 *to_raydium_rm67200(struct drm_panel *panel) +{ + return container_of(panel, struct raydium_rm67200, panel); +} + +static void raydium_rm67200_reset(struct raydium_rm67200 *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + msleep(60); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + msleep(60); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + msleep(60); +} + +static void raydium_rm67200_write(struct mipi_dsi_multi_context *ctx, + u8 arg1, u8 arg2) +{ + u8 d[] = { arg1, arg2 }; + + mipi_dsi_generic_write_multi(ctx, d, ARRAY_SIZE(d)); +} + +static void w552793baa_setup(struct mipi_dsi_multi_context *ctx) +{ + raydium_rm67200_write(ctx, 0xfe, 0x21); + raydium_rm67200_write(ctx, 0x04, 0x00); + raydium_rm67200_write(ctx, 0x00, 0x64); + raydium_rm67200_write(ctx, 0x2a, 0x00); + raydium_rm67200_write(ctx, 0x26, 0x64); + raydium_rm67200_write(ctx, 0x54, 0x00); + raydium_rm67200_write(ctx, 0x50, 0x64); + raydium_rm67200_write(ctx, 0x7b, 0x00); + raydium_rm67200_write(ctx, 0x77, 0x64); + raydium_rm67200_write(ctx, 0xa2, 0x00); + raydium_rm67200_write(ctx, 0x9d, 0x64); + raydium_rm67200_write(ctx, 0xc9, 0x00); + raydium_rm67200_write(ctx, 0xc5, 0x64); + raydium_rm67200_write(ctx, 0x01, 0x71); + raydium_rm67200_write(ctx, 0x27, 0x71); + raydium_rm67200_write(ctx, 0x51, 0x71); + raydium_rm67200_write(ctx, 0x78, 0x71); + raydium_rm67200_write(ctx, 0x9e, 0x71); + raydium_rm67200_write(ctx, 0xc6, 0x71); + raydium_rm67200_write(ctx, 0x02, 0x89); + raydium_rm67200_write(ctx, 0x28, 0x89); + raydium_rm67200_write(ctx, 0x52, 0x89); + raydium_rm67200_write(ctx, 0x79, 0x89); + raydium_rm67200_write(ctx, 0x9f, 0x89); + raydium_rm67200_write(ctx, 0xc7, 0x89); + raydium_rm67200_write(ctx, 0x03, 0x9e); + raydium_rm67200_write(ctx, 0x29, 0x9e); + raydium_rm67200_write(ctx, 0x53, 0x9e); + raydium_rm67200_write(ctx, 0x7a, 0x9e); + raydium_rm67200_write(ctx, 0xa0, 0x9e); + raydium_rm67200_write(ctx, 0xc8, 0x9e); + raydium_rm67200_write(ctx, 0x09, 0x00); + raydium_rm67200_write(ctx, 0x05, 0xb0); + raydium_rm67200_write(ctx, 0x31, 0x00); + raydium_rm67200_write(ctx, 0x2b, 0xb0); + raydium_rm67200_write(ctx, 0x5a, 0x00); + raydium_rm67200_write(ctx, 0x55, 0xb0); + raydium_rm67200_write(ctx, 0x80, 0x00); + raydium_rm67200_write(ctx, 0x7c, 0xb0); + raydium_rm67200_write(ctx, 0xa7, 0x00); + raydium_rm67200_write(ctx, 0xa3, 0xb0); + raydium_rm67200_write(ctx, 0xce, 0x00); + raydium_rm67200_write(ctx, 0xca, 0xb0); + raydium_rm67200_write(ctx, 0x06, 0xc0); + raydium_rm67200_write(ctx, 0x2d, 0xc0); + raydium_rm67200_write(ctx, 0x56, 0xc0); + raydium_rm67200_write(ctx, 0x7d, 0xc0); + raydium_rm67200_write(ctx, 0xa4, 0xc0); + raydium_rm67200_write(ctx, 0xcb, 0xc0); + raydium_rm67200_write(ctx, 0x07, 0xcf); + raydium_rm67200_write(ctx, 0x2f, 0xcf); + raydium_rm67200_write(ctx, 0x58, 0xcf); + raydium_rm67200_write(ctx, 0x7e, 0xcf); + raydium_rm67200_write(ctx, 0xa5, 0xcf); + raydium_rm67200_write(ctx, 0xcc, 0xcf); + raydium_rm67200_write(ctx, 0x08, 0xdd); + raydium_rm67200_write(ctx, 0x30, 0xdd); + raydium_rm67200_write(ctx, 0x59, 0xdd); + raydium_rm67200_write(ctx, 0x7f, 0xdd); + raydium_rm67200_write(ctx, 0xa6, 0xdd); + raydium_rm67200_write(ctx, 0xcd, 0xdd); + raydium_rm67200_write(ctx, 0x0e, 0x15); + raydium_rm67200_write(ctx, 0x0a, 0xe9); + raydium_rm67200_write(ctx, 0x36, 0x15); + raydium_rm67200_write(ctx, 0x32, 0xe9); + raydium_rm67200_write(ctx, 0x5f, 0x15); + raydium_rm67200_write(ctx, 0x5b, 0xe9); + raydium_rm67200_write(ctx, 0x85, 0x15); + raydium_rm67200_write(ctx, 0x81, 0xe9); + raydium_rm67200_write(ctx, 0xad, 0x15); + raydium_rm67200_write(ctx, 0xa9, 0xe9); + raydium_rm67200_write(ctx, 0xd3, 0x15); + raydium_rm67200_write(ctx, 0xcf, 0xe9); + raydium_rm67200_write(ctx, 0x0b, 0x14); + raydium_rm67200_write(ctx, 0x33, 0x14); + raydium_rm67200_write(ctx, 0x5c, 0x14); + raydium_rm67200_write(ctx, 0x82, 0x14); + raydium_rm67200_write(ctx, 0xaa, 0x14); + raydium_rm67200_write(ctx, 0xd0, 0x14); + raydium_rm67200_write(ctx, 0x0c, 0x36); + raydium_rm67200_write(ctx, 0x34, 0x36); + raydium_rm67200_write(ctx, 0x5d, 0x36); + raydium_rm67200_write(ctx, 0x83, 0x36); + raydium_rm67200_write(ctx, 0xab, 0x36); + raydium_rm67200_write(ctx, 0xd1, 0x36); + raydium_rm67200_write(ctx, 0x0d, 0x6b); + raydium_rm67200_write(ctx, 0x35, 0x6b); + raydium_rm67200_write(ctx, 0x5e, 0x6b); + raydium_rm67200_write(ctx, 0x84, 0x6b); + raydium_rm67200_write(ctx, 0xac, 0x6b); + raydium_rm67200_write(ctx, 0xd2, 0x6b); + raydium_rm67200_write(ctx, 0x13, 0x5a); + raydium_rm67200_write(ctx, 0x0f, 0x94); + raydium_rm67200_write(ctx, 0x3b, 0x5a); + raydium_rm67200_write(ctx, 0x37, 0x94); + raydium_rm67200_write(ctx, 0x64, 0x5a); + raydium_rm67200_write(ctx, 0x60, 0x94); + raydium_rm67200_write(ctx, 0x8a, 0x5a); + raydium_rm67200_write(ctx, 0x86, 0x94); + raydium_rm67200_write(ctx, 0xb2, 0x5a); + raydium_rm67200_write(ctx, 0xae, 0x94); + raydium_rm67200_write(ctx, 0xd8, 0x5a); + raydium_rm67200_write(ctx, 0xd4, 0x94); + raydium_rm67200_write(ctx, 0x10, 0xd1); + raydium_rm67200_write(ctx, 0x38, 0xd1); + raydium_rm67200_write(ctx, 0x61, 0xd1); + raydium_rm67200_write(ctx, 0x87, 0xd1); + raydium_rm67200_write(ctx, 0xaf, 0xd1); + raydium_rm67200_write(ctx, 0xd5, 0xd1); + raydium_rm67200_write(ctx, 0x11, 0x04); + raydium_rm67200_write(ctx, 0x39, 0x04); + raydium_rm67200_write(ctx, 0x62, 0x04); + raydium_rm67200_write(ctx, 0x88, 0x04); + raydium_rm67200_write(ctx, 0xb0, 0x04); + raydium_rm67200_write(ctx, 0xd6, 0x04); + raydium_rm67200_write(ctx, 0x12, 0x05); + raydium_rm67200_write(ctx, 0x3a, 0x05); + raydium_rm67200_write(ctx, 0x63, 0x05); + raydium_rm67200_write(ctx, 0x89, 0x05); + raydium_rm67200_write(ctx, 0xb1, 0x05); + raydium_rm67200_write(ctx, 0xd7, 0x05); + raydium_rm67200_write(ctx, 0x18, 0xaa); + raydium_rm67200_write(ctx, 0x14, 0x36); + raydium_rm67200_write(ctx, 0x42, 0xaa); + raydium_rm67200_write(ctx, 0x3d, 0x36); + raydium_rm67200_write(ctx, 0x69, 0xaa); + raydium_rm67200_write(ctx, 0x65, 0x36); + raydium_rm67200_write(ctx, 0x8f, 0xaa); + raydium_rm67200_write(ctx, 0x8b, 0x36); + raydium_rm67200_write(ctx, 0xb7, 0xaa); + raydium_rm67200_write(ctx, 0xb3, 0x36); + raydium_rm67200_write(ctx, 0xdd, 0xaa); + raydium_rm67200_write(ctx, 0xd9, 0x36); + raydium_rm67200_write(ctx, 0x15, 0x74); + raydium_rm67200_write(ctx, 0x3f, 0x74); + raydium_rm67200_write(ctx, 0x66, 0x74); + raydium_rm67200_write(ctx, 0x8c, 0x74); + raydium_rm67200_write(ctx, 0xb4, 0x74); + raydium_rm67200_write(ctx, 0xda, 0x74); + raydium_rm67200_write(ctx, 0x16, 0x9f); + raydium_rm67200_write(ctx, 0x40, 0x9f); + raydium_rm67200_write(ctx, 0x67, 0x9f); + raydium_rm67200_write(ctx, 0x8d, 0x9f); + raydium_rm67200_write(ctx, 0xb5, 0x9f); + raydium_rm67200_write(ctx, 0xdb, 0x9f); + raydium_rm67200_write(ctx, 0x17, 0xdc); + raydium_rm67200_write(ctx, 0x41, 0xdc); + raydium_rm67200_write(ctx, 0x68, 0xdc); + raydium_rm67200_write(ctx, 0x8e, 0xdc); + raydium_rm67200_write(ctx, 0xb6, 0xdc); + raydium_rm67200_write(ctx, 0xdc, 0xdc); + raydium_rm67200_write(ctx, 0x1d, 0xff); + raydium_rm67200_write(ctx, 0x19, 0x03); + raydium_rm67200_write(ctx, 0x47, 0xff); + raydium_rm67200_write(ctx, 0x43, 0x03); + raydium_rm67200_write(ctx, 0x6e, 0xff); + raydium_rm67200_write(ctx, 0x6a, 0x03); + raydium_rm67200_write(ctx, 0x94, 0xff); + raydium_rm67200_write(ctx, 0x90, 0x03); + raydium_rm67200_write(ctx, 0xbc, 0xff); + raydium_rm67200_write(ctx, 0xb8, 0x03); + raydium_rm67200_write(ctx, 0xe2, 0xff); + raydium_rm67200_write(ctx, 0xde, 0x03); + raydium_rm67200_write(ctx, 0x1a, 0x35); + raydium_rm67200_write(ctx, 0x44, 0x35); + raydium_rm67200_write(ctx, 0x6b, 0x35); + raydium_rm67200_write(ctx, 0x91, 0x35); + raydium_rm67200_write(ctx, 0xb9, 0x35); + raydium_rm67200_write(ctx, 0xdf, 0x35); + raydium_rm67200_write(ctx, 0x1b, 0x45); + raydium_rm67200_write(ctx, 0x45, 0x45); + raydium_rm67200_write(ctx, 0x6c, 0x45); + raydium_rm67200_write(ctx, 0x92, 0x45); + raydium_rm67200_write(ctx, 0xba, 0x45); + raydium_rm67200_write(ctx, 0xe0, 0x45); + raydium_rm67200_write(ctx, 0x1c, 0x55); + raydium_rm67200_write(ctx, 0x46, 0x55); + raydium_rm67200_write(ctx, 0x6d, 0x55); + raydium_rm67200_write(ctx, 0x93, 0x55); + raydium_rm67200_write(ctx, 0xbb, 0x55); + raydium_rm67200_write(ctx, 0xe1, 0x55); + raydium_rm67200_write(ctx, 0x22, 0xff); + raydium_rm67200_write(ctx, 0x1e, 0x68); + raydium_rm67200_write(ctx, 0x4c, 0xff); + raydium_rm67200_write(ctx, 0x48, 0x68); + raydium_rm67200_write(ctx, 0x73, 0xff); + raydium_rm67200_write(ctx, 0x6f, 0x68); + raydium_rm67200_write(ctx, 0x99, 0xff); + raydium_rm67200_write(ctx, 0x95, 0x68); + raydium_rm67200_write(ctx, 0xc1, 0xff); + raydium_rm67200_write(ctx, 0xbd, 0x68); + raydium_rm67200_write(ctx, 0xe7, 0xff); + raydium_rm67200_write(ctx, 0xe3, 0x68); + raydium_rm67200_write(ctx, 0x1f, 0x7e); + raydium_rm67200_write(ctx, 0x49, 0x7e); + raydium_rm67200_write(ctx, 0x70, 0x7e); + raydium_rm67200_write(ctx, 0x96, 0x7e); + raydium_rm67200_write(ctx, 0xbe, 0x7e); + raydium_rm67200_write(ctx, 0xe4, 0x7e); + raydium_rm67200_write(ctx, 0x20, 0x97); + raydium_rm67200_write(ctx, 0x4a, 0x97); + raydium_rm67200_write(ctx, 0x71, 0x97); + raydium_rm67200_write(ctx, 0x97, 0x97); + raydium_rm67200_write(ctx, 0xbf, 0x97); + raydium_rm67200_write(ctx, 0xe5, 0x97); + raydium_rm67200_write(ctx, 0x21, 0xb5); + raydium_rm67200_write(ctx, 0x4b, 0xb5); + raydium_rm67200_write(ctx, 0x72, 0xb5); + raydium_rm67200_write(ctx, 0x98, 0xb5); + raydium_rm67200_write(ctx, 0xc0, 0xb5); + raydium_rm67200_write(ctx, 0xe6, 0xb5); + raydium_rm67200_write(ctx, 0x25, 0xf0); + raydium_rm67200_write(ctx, 0x23, 0xe8); + raydium_rm67200_write(ctx, 0x4f, 0xf0); + raydium_rm67200_write(ctx, 0x4d, 0xe8); + raydium_rm67200_write(ctx, 0x76, 0xf0); + raydium_rm67200_write(ctx, 0x74, 0xe8); + raydium_rm67200_write(ctx, 0x9c, 0xf0); + raydium_rm67200_write(ctx, 0x9a, 0xe8); + raydium_rm67200_write(ctx, 0xc4, 0xf0); + raydium_rm67200_write(ctx, 0xc2, 0xe8); + raydium_rm67200_write(ctx, 0xea, 0xf0); + raydium_rm67200_write(ctx, 0xe8, 0xe8); + raydium_rm67200_write(ctx, 0x24, 0xff); + raydium_rm67200_write(ctx, 0x4e, 0xff); + raydium_rm67200_write(ctx, 0x75, 0xff); + raydium_rm67200_write(ctx, 0x9b, 0xff); + raydium_rm67200_write(ctx, 0xc3, 0xff); + raydium_rm67200_write(ctx, 0xe9, 0xff); + raydium_rm67200_write(ctx, 0xfe, 0x3d); + raydium_rm67200_write(ctx, 0x00, 0x04); + raydium_rm67200_write(ctx, 0xfe, 0x23); + raydium_rm67200_write(ctx, 0x08, 0x82); + raydium_rm67200_write(ctx, 0x0a, 0x00); + raydium_rm67200_write(ctx, 0x0b, 0x00); + raydium_rm67200_write(ctx, 0x0c, 0x01); + raydium_rm67200_write(ctx, 0x16, 0x00); + raydium_rm67200_write(ctx, 0x18, 0x02); + raydium_rm67200_write(ctx, 0x1b, 0x04); + raydium_rm67200_write(ctx, 0x19, 0x04); + raydium_rm67200_write(ctx, 0x1c, 0x81); + raydium_rm67200_write(ctx, 0x1f, 0x00); + raydium_rm67200_write(ctx, 0x20, 0x03); + raydium_rm67200_write(ctx, 0x23, 0x04); + raydium_rm67200_write(ctx, 0x21, 0x01); + raydium_rm67200_write(ctx, 0x54, 0x63); + raydium_rm67200_write(ctx, 0x55, 0x54); + raydium_rm67200_write(ctx, 0x6e, 0x45); + raydium_rm67200_write(ctx, 0x6d, 0x36); + raydium_rm67200_write(ctx, 0xfe, 0x3d); + raydium_rm67200_write(ctx, 0x55, 0x78); + raydium_rm67200_write(ctx, 0xfe, 0x20); + raydium_rm67200_write(ctx, 0x26, 0x30); + raydium_rm67200_write(ctx, 0xfe, 0x3d); + raydium_rm67200_write(ctx, 0x20, 0x71); + raydium_rm67200_write(ctx, 0x50, 0x8f); + raydium_rm67200_write(ctx, 0x51, 0x8f); + raydium_rm67200_write(ctx, 0xfe, 0x00); + raydium_rm67200_write(ctx, 0x35, 0x00); +} + +static int raydium_rm67200_prepare(struct drm_panel *panel) +{ + struct raydium_rm67200 *ctx = to_raydium_rm67200(panel); + int ret; + + ret = regulator_bulk_enable(ctx->num_supplies, ctx->supplies); + if (ret < 0) + return ret; + + raydium_rm67200_reset(ctx); + + msleep(60); + + return 0; +} + +static int raydium_rm67200_unprepare(struct drm_panel *panel) +{ + struct raydium_rm67200 *ctx = to_raydium_rm67200(panel); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ctx->num_supplies, ctx->supplies); + + msleep(60); + + return 0; +} + +static int raydium_rm67200_enable(struct drm_panel *panel) +{ + struct raydium_rm67200 *rm67200 = to_raydium_rm67200(panel); + struct mipi_dsi_multi_context ctx = { .dsi = rm67200->dsi }; + + rm67200->panel_info->panel_setup(&ctx); + mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); + mipi_dsi_msleep(&ctx, 120); + mipi_dsi_dcs_set_display_on_multi(&ctx); + mipi_dsi_msleep(&ctx, 30); + + return ctx.accum_err; +} + +static int raydium_rm67200_disable(struct drm_panel *panel) +{ + struct raydium_rm67200 *rm67200 = to_raydium_rm67200(panel); + struct mipi_dsi_multi_context ctx = { .dsi = rm67200->dsi }; + + mipi_dsi_dcs_set_display_off_multi(&ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); + mipi_dsi_msleep(&ctx, 60); + + return ctx.accum_err; +} + +static int raydium_rm67200_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct raydium_rm67200 *ctx = to_raydium_rm67200(panel); + + return drm_connector_helper_get_modes_fixed(connector, &ctx->panel_info->mode); +} + +static const struct drm_panel_funcs raydium_rm67200_funcs = { + .prepare = raydium_rm67200_prepare, + .unprepare = raydium_rm67200_unprepare, + .get_modes = raydium_rm67200_get_modes, + .enable = raydium_rm67200_enable, + .disable = raydium_rm67200_disable, +}; + +static int raydium_rm67200_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct raydium_rm67200 *ctx; + int ret = 0; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->panel_info = device_get_match_data(dev); + if (!ctx->panel_info) + return -EINVAL; + + ctx->num_supplies = ctx->panel_info->num_regulators; + ret = devm_regulator_bulk_get_const(&dsi->dev, + ctx->panel_info->num_regulators, + ctx->panel_info->regulators, + &ctx->supplies); + if (ret < 0) + return ret; + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi = dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + ctx->panel.prepare_prev_first = true; + + drm_panel_init(&ctx->panel, dev, &raydium_rm67200_funcs, + DRM_MODE_CONNECTOR_DSI); + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return ret; + + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err(dev, "Failed to attach to DSI host: %d\n", ret); + drm_panel_remove(&ctx->panel); + } + + return ret; +} + +static void raydium_rm67200_remove(struct mipi_dsi_device *dsi) +{ + struct raydium_rm67200 *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); +} + +static const struct regulator_bulk_data w552793baa_regulators[] = { + { .supply = "vdd", }, /* 2.8V */ + { .supply = "iovcc", }, /* 1.8V */ + { .supply = "vsp", }, /* +5.5V */ + { .supply = "vsn", }, /* -5.5V */ +}; + +static const struct raydium_rm67200_panel_info w552793baa_info = { + .mode = { + .clock = 132000, + .hdisplay = 1080, + .hsync_start = 1095, + .hsync_end = 1125, + .htotal = 1129, + .vdisplay = 1920, + .vsync_start = 1935, + .vsync_end = 1950, + .vtotal = 1952, + .width_mm = 68, /* 68.04mm */ + .height_mm = 121, /* 120.96mm */ + .type = DRM_MODE_TYPE_DRIVER, + }, + .regulators = w552793baa_regulators, + .num_regulators = ARRAY_SIZE(w552793baa_regulators), + .panel_setup = w552793baa_setup, +}; + +static const struct of_device_id raydium_rm67200_of_match[] = { + { .compatible = "wanchanglong,w552793baa", .data = &w552793baa_info }, + { /*sentinel*/ } +}; +MODULE_DEVICE_TABLE(of, raydium_rm67200_of_match); + +static struct mipi_dsi_driver raydium_rm67200_driver = { + .probe = raydium_rm67200_probe, + .remove = raydium_rm67200_remove, + .driver = { + .name = "panel-raydium-rm67200", + .of_match_table = raydium_rm67200_of_match, + }, +}; +module_mipi_dsi_driver(raydium_rm67200_driver); + +MODULE_AUTHOR("Sebastian Reichel <sebastian.reichel@collabora.com>"); +MODULE_DESCRIPTION("DRM driver for RM67200-equipped DSI panels"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c b/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c index d2df227abbea..57b1a899bbdc 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c @@ -39,91 +39,66 @@ static void s6e88a0_ams452ef01_reset(struct s6e88a0_ams452ef01 *ctx) static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands - mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcc, 0x4c); // set Pixel Clock Divider polarity - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); // set default brightness/gama - mipi_dsi_dcs_write_seq(dsi, 0xca, - 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB - 0x80, 0x80, 0x80, // V203 R,G,B - 0x80, 0x80, 0x80, // V151 R,G,B - 0x80, 0x80, 0x80, // V87 R,G,B - 0x80, 0x80, 0x80, // V51 R,G,B - 0x80, 0x80, 0x80, // V35 R,G,B - 0x80, 0x80, 0x80, // V23 R,G,B - 0x80, 0x80, 0x80, // V11 R,G,B - 0x6b, 0x68, 0x71, // V3 R,G,B - 0x00, 0x00, 0x00); // V1 R,G,B + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, + 0x01, 0x00, 0x01, 0x00, 0x01, 0x00,// V255 RR,GG,BB + 0x80, 0x80, 0x80, // V203 R,G,B + 0x80, 0x80, 0x80, // V151 R,G,B + 0x80, 0x80, 0x80, // V87 R,G,B + 0x80, 0x80, 0x80, // V51 R,G,B + 0x80, 0x80, 0x80, // V35 R,G,B + 0x80, 0x80, 0x80, // V23 R,G,B + 0x80, 0x80, 0x80, // V11 R,G,B + 0x6b, 0x68, 0x71, // V3 R,G,B + 0x00, 0x00, 0x00); // V1 R,G,B // set default Amoled Off Ratio - mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); - mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update - mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0x2c, 0x0b); // set default elvss voltage + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf7, 0x03); // gamma/aor update + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display on: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - return 0; + return dsi_ctx.accum_err; } -static int s6e88a0_ams452ef01_off(struct s6e88a0_ams452ef01 *ctx) +static void s6e88a0_ams452ef01_off(struct s6e88a0_ams452ef01 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi}; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - msleep(35); - - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(120); - - return 0; + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 35); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); } static int s6e88a0_ams452ef01_prepare(struct drm_panel *panel) { struct s6e88a0_ams452ef01 *ctx = to_s6e88a0_ams452ef01(panel); - struct device *dev = &ctx->dsi->dev; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - if (ret < 0) { - dev_err(dev, "Failed to enable regulators: %d\n", ret); + if (ret < 0) return ret; - } s6e88a0_ams452ef01_reset(ctx); ret = s6e88a0_ams452ef01_on(ctx); if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); gpiod_set_value_cansleep(ctx->reset_gpio, 0); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); @@ -136,12 +111,8 @@ static int s6e88a0_ams452ef01_prepare(struct drm_panel *panel) static int s6e88a0_ams452ef01_unprepare(struct drm_panel *panel) { struct s6e88a0_ams452ef01 *ctx = to_s6e88a0_ams452ef01(panel); - struct device *dev = &ctx->dsi->dev; - int ret; - ret = s6e88a0_ams452ef01_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + s6e88a0_ams452ef01_off(ctx); gpiod_set_value_cansleep(ctx->reset_gpio, 0); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); diff --git a/drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c b/drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c index 74c760ee0c2d..0b4e0983639b 100644 --- a/drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c +++ b/drivers/gpu/drm/panel/panel-sharp-ls060t1sx01.c @@ -44,60 +44,39 @@ static void sharp_ls060_reset(struct sharp_ls060 *ctx) static int sharp_ls060_on(struct sharp_ls060 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x13); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbb, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_MEMORY_START); - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display on: %d\n", ret); - return ret; - } - msleep(50); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 50); - return 0; + return dsi_ctx.accum_err; } -static int sharp_ls060_off(struct sharp_ls060 *ctx) +static void sharp_ls060_off(struct sharp_ls060 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - usleep_range(2000, 3000); - - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(121); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 2000, 3000); - return 0; + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 121); } static int sharp_ls060_prepare(struct drm_panel *panel) { struct sharp_ls060 *ctx = to_sharp_ls060(panel); - struct device *dev = &ctx->dsi->dev; int ret; ret = regulator_enable(ctx->vddi_supply); @@ -125,10 +104,8 @@ static int sharp_ls060_prepare(struct drm_panel *panel) sharp_ls060_reset(ctx); ret = sharp_ls060_on(ctx); - if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); + if (ret < 0) goto err_on; - } return 0; @@ -154,12 +131,8 @@ err_avdd: static int sharp_ls060_unprepare(struct drm_panel *panel) { struct sharp_ls060 *ctx = to_sharp_ls060(panel); - struct device *dev = &ctx->dsi->dev; - int ret; - ret = sharp_ls060_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + sharp_ls060_off(ctx); regulator_disable(ctx->vddh_supply); diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 9b2f128fd309..232b03c1a259 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1374,6 +1374,64 @@ static const struct panel_desc bananapi_s070wv20_ct16 = { }, }; +static const struct display_timing boe_av101hdt_a10_timing = { + .pixelclock = { 74210000, 75330000, 76780000, }, + .hactive = { 1280, 1280, 1280, }, + .hfront_porch = { 10, 42, 33, }, + .hback_porch = { 10, 18, 33, }, + .hsync_len = { 30, 10, 30, }, + .vactive = { 720, 720, 720, }, + .vfront_porch = { 200, 183, 200, }, + .vback_porch = { 8, 8, 8, }, + .vsync_len = { 2, 19, 2, }, + .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, +}; + +static const struct panel_desc boe_av101hdt_a10 = { + .timings = &boe_av101hdt_a10_timing, + .num_timings = 1, + .bpc = 8, + .size = { + .width = 224, + .height = 126, + }, + .delay = { + .enable = 50, + .disable = 50, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + .connector_type = DRM_MODE_CONNECTOR_LVDS, +}; + +static const struct display_timing boe_av123z7m_n17_timing = { + .pixelclock = { 86600000, 88000000, 90800000, }, + .hactive = { 1920, 1920, 1920, }, + .hfront_porch = { 10, 10, 10, }, + .hback_porch = { 10, 10, 10, }, + .hsync_len = { 9, 12, 25, }, + .vactive = { 720, 720, 720, }, + .vfront_porch = { 7, 10, 13, }, + .vback_porch = { 7, 10, 13, }, + .vsync_len = { 7, 11, 14, }, + .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, +}; + +static const struct panel_desc boe_av123z7m_n17 = { + .timings = &boe_av123z7m_n17_timing, + .bpc = 8, + .num_timings = 1, + .size = { + .width = 292, + .height = 110, + }, + .delay = { + .prepare = 50, + .disable = 50, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + .connector_type = DRM_MODE_CONNECTOR_LVDS, +}; + static const struct drm_display_mode boe_bp101wx1_100_mode = { .clock = 78945, .hdisplay = 1280, @@ -4814,6 +4872,12 @@ static const struct of_device_id platform_of_match[] = { .compatible = "bananapi,s070wv20-ct16", .data = &bananapi_s070wv20_ct16, }, { + .compatible = "boe,av101hdt-a10", + .data = &boe_av101hdt_a10, + }, { + .compatible = "boe,av123z7m-n17", + .data = &boe_av123z7m_n17, + }, { .compatible = "boe,bp082wx1-100", .data = &boe_bp082wx1_100, }, { diff --git a/drivers/gpu/drm/panel/panel-sony-td4353-jdi.c b/drivers/gpu/drm/panel/panel-sony-td4353-jdi.c index 472195d4bbbe..97f4bb4e1029 100644 --- a/drivers/gpu/drm/panel/panel-sony-td4353-jdi.c +++ b/drivers/gpu/drm/panel/panel-sony-td4353-jdi.c @@ -47,93 +47,40 @@ static inline struct sony_td4353_jdi *to_sony_td4353_jdi(struct drm_panel *panel static int sony_td4353_jdi_on(struct sony_td4353_jdi *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_column_address(dsi, 0x0000, 1080 - 1); - if (ret < 0) { - dev_err(dev, "Failed to set column address: %d\n", ret); - return ret; - } - - ret = mipi_dsi_dcs_set_page_address(dsi, 0x0000, 2160 - 1); - if (ret < 0) { - dev_err(dev, "Failed to set page address: %d\n", ret); - return ret; - } - - ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0); - if (ret < 0) { - dev_err(dev, "Failed to set tear scanline: %d\n", ret); - return ret; - } - - ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - if (ret < 0) { - dev_err(dev, "Failed to set tear on: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 1080 - 1); + mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 2160 - 1); + mipi_dsi_dcs_set_tear_scanline_multi(&dsi_ctx, 0); + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00); - - ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x77); - if (ret < 0) { - dev_err(dev, "Failed to set pixel format: %d\n", ret); - return ret; - } - - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, - 0x00, 0x00, 0x08, 0x6f); - - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(70); + mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_PARTIAL_ROWS, + 0x00, 0x00, 0x08, 0x6f); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_MEMORY_START); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to turn display on: %d\n", ret); - return ret; - } - - return 0; + return dsi_ctx.accum_err; } -static int sony_td4353_jdi_off(struct sony_td4353_jdi *ctx) +static void sony_td4353_jdi_off(struct sony_td4353_jdi *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - msleep(22); - - ret = mipi_dsi_dcs_set_tear_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set tear off: %d\n", ret); - return ret; - } - - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(80); - - return 0; + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 22); + mipi_dsi_dcs_set_tear_off_multi(&dsi_ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 80); } static void sony_td4353_assert_reset_gpios(struct sony_td4353_jdi *ctx, int mode) @@ -146,14 +93,11 @@ static void sony_td4353_assert_reset_gpios(struct sony_td4353_jdi *ctx, int mode static int sony_td4353_jdi_prepare(struct drm_panel *panel) { struct sony_td4353_jdi *ctx = to_sony_td4353_jdi(panel); - struct device *dev = &ctx->dsi->dev; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - if (ret < 0) { - dev_err(dev, "Failed to enable regulators: %d\n", ret); + if (ret < 0) return ret; - } msleep(100); @@ -161,7 +105,6 @@ static int sony_td4353_jdi_prepare(struct drm_panel *panel) ret = sony_td4353_jdi_on(ctx); if (ret < 0) { - dev_err(dev, "Failed to power on panel: %d\n", ret); sony_td4353_assert_reset_gpios(ctx, 0); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); return ret; @@ -173,12 +116,8 @@ static int sony_td4353_jdi_prepare(struct drm_panel *panel) static int sony_td4353_jdi_unprepare(struct drm_panel *panel) { struct sony_td4353_jdi *ctx = to_sony_td4353_jdi(panel); - struct device *dev = &ctx->dsi->dev; - int ret; - ret = sony_td4353_jdi_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to power off panel: %d\n", ret); + sony_td4353_jdi_off(ctx); sony_td4353_assert_reset_gpios(ctx, 0); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); diff --git a/drivers/gpu/drm/panel/panel-summit.c b/drivers/gpu/drm/panel/panel-summit.c new file mode 100644 index 000000000000..e780faee1857 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-summit.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/backlight.h> +#include <drm/drm_device.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_mode.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> +#include <video/mipi_display.h> + +struct summit_data { + struct mipi_dsi_device *dsi; + struct backlight_device *bl; + struct drm_panel panel; +}; + +static int summit_set_brightness(struct device *dev) +{ + struct summit_data *s_data = dev_get_drvdata(dev); + int level = backlight_get_brightness(s_data->bl); + + return mipi_dsi_dcs_set_display_brightness(s_data->dsi, level); +} + +static int summit_bl_update_status(struct backlight_device *dev) +{ + return summit_set_brightness(&dev->dev); +} + +static const struct backlight_ops summit_bl_ops = { + .update_status = summit_bl_update_status, +}; + +static struct drm_display_mode summit_mode = { + .vdisplay = 2008, + .hdisplay = 60, + .hsync_start = 60 + 8, + .hsync_end = 60 + 8 + 80, + .htotal = 60 + 8 + 80 + 40, + .vsync_start = 2008 + 1, + .vsync_end = 2008 + 1 + 15, + .vtotal = 2008 + 1 + 15 + 6, + .clock = ((60 + 8 + 80 + 40) * (2008 + 1 + 15 + 6) * 60) / 1000, + .type = DRM_MODE_TYPE_DRIVER, + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, +}; + +static int summit_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + connector->display_info.non_desktop = true; + drm_object_property_set_value(&connector->base, + connector->dev->mode_config.non_desktop_property, + connector->display_info.non_desktop); + + return drm_connector_helper_get_modes_fixed(connector, &summit_mode); +} + +static const struct drm_panel_funcs summit_panel_funcs = { + .get_modes = summit_get_modes, +}; + +static int summit_probe(struct mipi_dsi_device *dsi) +{ + struct backlight_properties props = { 0 }; + struct device *dev = &dsi->dev; + struct summit_data *s_data; + int ret; + + s_data = devm_kzalloc(dev, sizeof(*s_data), GFP_KERNEL); + if (!s_data) + return -ENOMEM; + + mipi_dsi_set_drvdata(dsi, s_data); + s_data->dsi = dsi; + + ret = device_property_read_u32(dev, "max-brightness", &props.max_brightness); + if (ret) + return ret; + props.type = BACKLIGHT_RAW; + + s_data->bl = devm_backlight_device_register(dev, dev_name(dev), + dev, s_data, &summit_bl_ops, &props); + if (IS_ERR(s_data->bl)) + return PTR_ERR(s_data->bl); + + drm_panel_init(&s_data->panel, dev, &summit_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + drm_panel_add(&s_data->panel); + + return mipi_dsi_attach(dsi); +} + +static void summit_remove(struct mipi_dsi_device *dsi) +{ + struct summit_data *s_data = mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(dsi); + drm_panel_remove(&s_data->panel); +} + +static int summit_suspend(struct device *dev) +{ + struct summit_data *s_data = dev_get_drvdata(dev); + + return mipi_dsi_dcs_set_display_brightness(s_data->dsi, 0); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(summit_pm_ops, summit_suspend, + summit_set_brightness); + +static const struct of_device_id summit_of_match[] = { + { .compatible = "apple,summit" }, + {}, +}; + +MODULE_DEVICE_TABLE(of, summit_of_match); + +static struct mipi_dsi_driver summit_driver = { + .probe = summit_probe, + .remove = summit_remove, + .driver = { + .name = "panel-summit", + .of_match_table = summit_of_match, + .pm = pm_sleep_ptr(&summit_pm_ops), + }, +}; +module_mipi_dsi_driver(summit_driver); + +MODULE_DESCRIPTION("Summit Display Panel Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/panel/panel-visionox-r66451.c b/drivers/gpu/drm/panel/panel-visionox-r66451.c index 493f2a6076f8..3ea0a86f6e69 100644 --- a/drivers/gpu/drm/panel/panel-visionox-r66451.c +++ b/drivers/gpu/drm/panel/panel-visionox-r66451.c @@ -42,85 +42,84 @@ static void visionox_r66451_reset(struct visionox_r66451 *ctx) static int visionox_r66451_on(struct visionox_r66451 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xc2, - 0x09, 0x24, 0x0c, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, - 0x09, 0x3c); - mipi_dsi_dcs_write_seq(dsi, 0xd7, - 0x00, 0xb9, 0x3c, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a, - 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, - 0x3c, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a); - mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x80); - mipi_dsi_dcs_write_seq(dsi, 0xde, - 0x40, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, - 0x10, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x02, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0xe8, 0x00, 0x02); - mipi_dsi_dcs_write_seq(dsi, 0xe4, 0x00, 0x08); - mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xc4, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x32); - mipi_dsi_dcs_write_seq(dsi, 0xcf, - 0x64, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, - 0x00, 0x0b, 0x77, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x02, 0x02, 0x02, 0x02, 0x02, 0x03); - mipi_dsi_dcs_write_seq(dsi, 0xd3, - 0x45, 0x00, 0x00, 0x01, 0x13, 0x15, 0x00, 0x15, 0x07, - 0x0f, 0x77, 0x77, 0x77, 0x37, 0xb2, 0x11, 0x00, 0xa0, - 0x3c, 0x9c); - mipi_dsi_dcs_write_seq(dsi, 0xd7, - 0x00, 0xb9, 0x34, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a, - 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, - 0x34, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a); - mipi_dsi_dcs_write_seq(dsi, 0xd8, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x3a, 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x3a, - 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, - 0x00, 0x32, 0x00, 0x0a, 0x00, 0x22); - mipi_dsi_dcs_write_seq(dsi, 0xdf, - 0x50, 0x42, 0x58, 0x81, 0x2d, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x01, 0x0f, 0xff, 0xd4, 0x0e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0f, 0x53, 0xf1, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x80); - mipi_dsi_dcs_write_seq(dsi, 0xe4, 0x34, 0xb4, 0x00, 0x00, 0x00, 0x39, 0x04, 0x09, 0x34); - mipi_dsi_dcs_write_seq(dsi, 0xe6, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x50, 0x40); - mipi_dsi_dcs_write_seq(dsi, 0xf3, 0x50, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xf2, 0x11); - mipi_dsi_dcs_write_seq(dsi, 0xf3, 0x01, 0x00, 0x00, 0x00, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xf4, 0x00, 0x02); - mipi_dsi_dcs_write_seq(dsi, 0xf2, 0x19); - mipi_dsi_dcs_write_seq(dsi, 0xdf, 0x50, 0x42); - mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - mipi_dsi_dcs_set_column_address(dsi, 0, 1080 - 1); - mipi_dsi_dcs_set_page_address(dsi, 0, 2340 - 1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, + 0x09, 0x24, 0x0c, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, + 0x09, 0x3c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd7, + 0x00, 0xb9, 0x3c, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, + 0x3c, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, + 0x40, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, + 0x10, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x02, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe8, 0x00, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe4, 0x00, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcf, + 0x64, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x00, 0x0b, 0x77, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x02, 0x02, 0x02, 0x02, 0x02, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd3, + 0x45, 0x00, 0x00, 0x01, 0x13, 0x15, 0x00, 0x15, 0x07, + 0x0f, 0x77, 0x77, 0x77, 0x37, 0xb2, 0x11, 0x00, 0xa0, + 0x3c, 0x9c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd7, + 0x00, 0xb9, 0x34, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, + 0x34, 0x00, 0x40, 0x04, 0x00, 0xa0, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd8, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x3a, 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x3a, + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, + 0x00, 0x32, 0x00, 0x0a, 0x00, 0x22); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdf, + 0x50, 0x42, 0x58, 0x81, 0x2d, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x01, 0x0f, 0xff, 0xd4, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0f, 0x53, 0xf1, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf7, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe4, 0x34, 0xb4, 0x00, 0x00, 0x00, 0x39, + 0x04, 0x09, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdf, 0x50, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x50, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf2, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x01, 0x00, 0x00, 0x00, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x00, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf2, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xdf, 0x50, 0x42); + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0, 1080 - 1); + mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0, 2340 - 1); dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - return 0; + return dsi_ctx.accum_err; } -static int visionox_r66451_off(struct visionox_r66451 *ctx) +static void visionox_r66451_off(struct visionox_r66451 *ctx) { ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - return 0; } static int visionox_r66451_prepare(struct drm_panel *panel) { struct visionox_r66451 *ctx = to_visionox_r66451(panel); - struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), @@ -132,7 +131,6 @@ static int visionox_r66451_prepare(struct drm_panel *panel) ret = visionox_r66451_on(ctx); if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); gpiod_set_value_cansleep(ctx->reset_gpio, 1); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); return ret; @@ -146,12 +144,8 @@ static int visionox_r66451_prepare(struct drm_panel *panel) static int visionox_r66451_unprepare(struct drm_panel *panel) { struct visionox_r66451 *ctx = to_visionox_r66451(panel); - struct device *dev = &ctx->dsi->dev; - int ret; - ret = visionox_r66451_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + visionox_r66451_off(ctx); gpiod_set_value_cansleep(ctx->reset_gpio, 1); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); @@ -179,7 +173,7 @@ static int visionox_r66451_enable(struct drm_panel *panel) struct visionox_r66451 *ctx = to_visionox_r66451(panel); struct mipi_dsi_device *dsi = ctx->dsi; struct drm_dsc_picture_parameter_set pps; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; if (!dsi->dsc) { dev_err(&dsi->dev, "DSC not attached to DSI\n"); @@ -187,51 +181,30 @@ static int visionox_r66451_enable(struct drm_panel *panel) } drm_dsc_pps_payload_pack(&pps, dsi->dsc); - ret = mipi_dsi_picture_parameter_set(dsi, &pps); - if (ret) { - dev_err(&dsi->dev, "Failed to set PPS\n"); - return ret; - } + mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps); - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(&dsi->dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(&dsi->dev, "Failed on set display on: %d\n", ret); - return ret; - } - msleep(20); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); - return 0; + return dsi_ctx.accum_err; } static int visionox_r66451_disable(struct drm_panel *panel) { struct visionox_r66451 *ctx = to_visionox_r66451(panel); struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - msleep(20); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); - return 0; + return dsi_ctx.accum_err; } static int visionox_r66451_get_modes(struct drm_panel *panel, diff --git a/drivers/gpu/drm/panel/panel-visionox-rm692e5.c b/drivers/gpu/drm/panel/panel-visionox-rm692e5.c new file mode 100644 index 000000000000..4db7fa8d74c4 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-visionox-rm692e5.c @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree: + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2025, Eugene Lepshy <fekz115@gmail.com> + * Copyright (c) 2025, Danila Tikhonov <danila@jiaxyga.com> + */ + +#include <linux/backlight.h> +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/regulator/consumer.h> + +#include <video/mipi_display.h> + +#include <drm/display/drm_dsc.h> +#include <drm/display/drm_dsc_helper.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> + +struct visionox_rm692e5 { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct drm_dsc_config dsc; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data *supplies; +}; + +static const struct regulator_bulk_data visionox_rm692e5_supplies[] = { + { .supply = "vddio" }, /* 1p8 */ + { .supply = "vdd" }, /* 3p3 */ +}; + +static inline +struct visionox_rm692e5 *to_visionox_rm692e5(struct drm_panel *panel) +{ + return container_of(panel, struct visionox_rm692e5, panel); +} + +static void visionox_rm692e5_reset(struct visionox_rm692e5 *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(1000, 2000); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + msleep(32); +} + +static int visionox_rm692e5_on(struct visionox_rm692e5 *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbd, 0x07); + mipi_dsi_usleep_range(&dsi_ctx, 17000, 18000); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd2); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x11); + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ab); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x60); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0xe8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x18); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0xf0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x1c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x69); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x79); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x7b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x7d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x7e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x83, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x22); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x85, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x86, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x87, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x88, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x89, 0xbe); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8a, 0x3a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8b, 0xfc); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8c, 0x3a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8d, 0xfa); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8e, 0x3a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8f, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x3b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x91, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x92, 0x3b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x93, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x3b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x95, 0xb6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x96, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x97, 0xf6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x98, 0x4c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x99, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9a, 0x4c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9b, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9c, 0x5c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9d, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9e, 0x8c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9f, 0xf4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_READ_PPS_START, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa3, 0x1c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa4, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa5, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa6, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa7, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_READ_PPS_CONTINUE, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xaa, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa0, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xa1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x6b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xce, 0xbb); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfa, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x08); + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x000d); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 50); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + + return dsi_ctx.accum_err; +} + +static int visionox_rm692e5_disable(struct drm_panel *panel) +{ + struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel); + struct mipi_dsi_device *dsi = ctx->dsi; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 1000, 2000); + + return dsi_ctx.accum_err; +} + +static int visionox_rm692e5_prepare(struct drm_panel *panel) +{ + struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel); + struct drm_dsc_picture_parameter_set pps; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(visionox_rm692e5_supplies), + ctx->supplies); + if (ret < 0) + return ret; + + visionox_rm692e5_reset(ctx); + + ret = visionox_rm692e5_on(ctx); + if (ret < 0) { + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + goto err; + } + + drm_dsc_pps_payload_pack(&pps, &ctx->dsc); + mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps); + mipi_dsi_compression_mode_ext_multi(&dsi_ctx, true, MIPI_DSI_COMPRESSION_DSC, 0); + + mipi_dsi_msleep(&dsi_ctx, 28); + + if (dsi_ctx.accum_err < 0) { + ret = dsi_ctx.accum_err; + goto err; + } + + return dsi_ctx.accum_err; +err: + regulator_bulk_disable(ARRAY_SIZE(visionox_rm692e5_supplies), + ctx->supplies); + return ret; +} + +static int visionox_rm692e5_unprepare(struct drm_panel *panel) +{ + struct visionox_rm692e5 *ctx = to_visionox_rm692e5(panel); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(visionox_rm692e5_supplies), + ctx->supplies); + + return 0; +} + +static const struct drm_display_mode visionox_rm692e5_modes[] = { + /* Let's initialize the highest frequency first */ + { /* 120Hz mode */ + .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 120 / 1000, + .hdisplay = 1080, + .hsync_start = 1080 + 26, + .hsync_end = 1080 + 26 + 39, + .htotal = 1080 + 26 + 39 + 36, + .vdisplay = 2400, + .vsync_start = 2400 + 16, + .vsync_end = 2400 + 16 + 21, + .vtotal = 2400 + 16 + 21 + 16, + .width_mm = 68, + .height_mm = 152, + .type = DRM_MODE_TYPE_DRIVER, + }, + { /* 90Hz mode */ + .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 90 / 1000, + .hdisplay = 1080, + .hsync_start = 1080 + 26, + .hsync_end = 1080 + 26 + 39, + .htotal = 1080 + 26 + 39 + 36, + .vdisplay = 2400, + .vsync_start = 2400 + 16, + .vsync_end = 2400 + 16 + 21, + .vtotal = 2400 + 16 + 21 + 16, + .width_mm = 68, + .height_mm = 152, + .type = DRM_MODE_TYPE_DRIVER, + }, + { /* 60Hz mode */ + .clock = (1080 + 26 + 39 + 36) * (2400 + 16 + 21 + 16) * 60 / 1000, + .hdisplay = 1080, + .hsync_start = 1080 + 26, + .hsync_end = 1080 + 26 + 39, + .htotal = 1080 + 26 + 39 + 36, + .vdisplay = 2400, + .vsync_start = 2400 + 16, + .vsync_end = 2400 + 16 + 21, + .vtotal = 2400 + 16 + 21 + 16, + .width_mm = 68, + .height_mm = 152, + .type = DRM_MODE_TYPE_DRIVER, + }, +}; + +static int visionox_rm692e5_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + int count = 0; + + for (int i = 0; i < ARRAY_SIZE(visionox_rm692e5_modes); i++) + count += drm_connector_helper_get_modes_fixed(connector, + &visionox_rm692e5_modes[i]); + + return count; +} + +static const struct drm_panel_funcs visionox_rm692e5_panel_funcs = { + .prepare = visionox_rm692e5_prepare, + .unprepare = visionox_rm692e5_unprepare, + .disable = visionox_rm692e5_disable, + .get_modes = visionox_rm692e5_get_modes, +}; + +static int visionox_rm692e5_bl_update_status(struct backlight_device *bl) +{ + struct mipi_dsi_device *dsi = bl_get_data(bl); + u16 brightness = backlight_get_brightness(bl); + int ret; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness); + if (ret < 0) + return ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + return 0; +} + +static int visionox_rm692e5_bl_get_brightness(struct backlight_device *bl) +{ + struct mipi_dsi_device *dsi = bl_get_data(bl); + u16 brightness; + int ret; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness); + if (ret < 0) + return ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + return brightness; +} + +static const struct backlight_ops visionox_rm692e5_bl_ops = { + .update_status = visionox_rm692e5_bl_update_status, + .get_brightness = visionox_rm692e5_bl_get_brightness, +}; + +static struct backlight_device * +visionox_rm692e5_create_backlight(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + const struct backlight_properties props = { + .type = BACKLIGHT_RAW, + .brightness = 2047, + .max_brightness = 4095, + }; + + return devm_backlight_device_register(dev, dev_name(dev), dev, dsi, + &visionox_rm692e5_bl_ops, &props); +} + +static int visionox_rm692e5_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct visionox_rm692e5 *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ret = devm_regulator_bulk_get_const(&dsi->dev, + ARRAY_SIZE(visionox_rm692e5_supplies), + visionox_rm692e5_supplies, + &ctx->supplies); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi = dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS; + + drm_panel_init(&ctx->panel, dev, &visionox_rm692e5_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + ctx->panel.prepare_prev_first = true; + + ctx->panel.backlight = visionox_rm692e5_create_backlight(dsi); + if (IS_ERR(ctx->panel.backlight)) + return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight), + "Failed to create backlight\n"); + + drm_panel_add(&ctx->panel); + + dsi->dsc = &ctx->dsc; + ctx->dsc.dsc_version_major = 1; + ctx->dsc.dsc_version_minor = 1; + ctx->dsc.slice_height = 20; + ctx->dsc.slice_width = 540; + ctx->dsc.slice_count = 1080 / ctx->dsc.slice_width; + ctx->dsc.bits_per_component = 10; + ctx->dsc.bits_per_pixel = 8 << 4; + ctx->dsc.block_pred_enable = true; + + ret = devm_mipi_dsi_attach(dev, dsi); + if (ret < 0) { + drm_panel_remove(&ctx->panel); + return dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); + } + + return 0; +} + +static void visionox_rm692e5_remove(struct mipi_dsi_device *dsi) +{ + struct visionox_rm692e5 *ctx = mipi_dsi_get_drvdata(dsi); + + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id visionox_rm692e5_of_match[] = { + { .compatible = "visionox,rm692e5" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, visionox_rm692e5_of_match); + +static struct mipi_dsi_driver visionox_rm692e5_driver = { + .probe = visionox_rm692e5_probe, + .remove = visionox_rm692e5_remove, + .driver = { + .name = "panel-visionox-rm692e5", + .of_match_table = visionox_rm692e5_of_match, + }, +}; +module_mipi_dsi_driver(visionox_rm692e5_driver); + +MODULE_AUTHOR("Eugene Lepshy <fekz115@gmail.com>"); +MODULE_AUTHOR("Danila Tikhonov <danila@jiaxyga.com>"); +MODULE_DESCRIPTION("DRM driver for Visionox RM692E5 cmd mode dsi panel"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c b/drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c index 22a14006765e..2b91414c2829 100644 --- a/drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c +++ b/drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c @@ -59,91 +59,80 @@ static inline struct xpp055c272 *panel_to_xpp055c272(struct drm_panel *panel) return container_of(panel, struct xpp055c272, panel); } -static int xpp055c272_init_sequence(struct xpp055c272 *ctx) +static void xpp055c272_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - struct device *dev = ctx->dev; - /* * Init sequence was supplied by the panel vendor without much * documentation. */ - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETMIPI, - 0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25, - 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01, - 0x00, 0x00, 0x37); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETRGBIF, - 0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00, - 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETSCR, - 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70, - 0x00); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEQ, - 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00, - 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER, - 0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd, - 0x67, 0x77, 0x33, 0x33); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff, - 0xff, 0x01, 0xff); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETBGP, 0x09, 0x09); - msleep(20); - - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVCOM, 0x87, 0x95); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP1, - 0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12, - 0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18, - 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, - 0x01, 0x00, 0x00, 0x00, 0x48, 0xf8, 0x86, 0x42, - 0x08, 0x88, 0x88, 0x80, 0x88, 0x88, 0x88, 0x58, - 0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88, - 0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP2, - 0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35, - 0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f, - 0x88, 0x80, 0x24, 0x68, 0x88, 0x88, 0x84, 0x88, - 0x88, 0x88, 0x23, 0x10, 0x00, 0x00, 0x1c, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05, - 0xa0, 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGAMMA, - 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36, - 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11, - 0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, - 0x36, 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, - 0x11, 0x18); - - msleep(60); - - dev_dbg(dev, "Panel init sequence done\n"); - return 0; + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETMIPI, + 0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25, + 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01, + 0x00, 0x00, 0x37); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPOWER_EXT, 0x25); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETRGBIF, + 0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00, + 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETSCR, + 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70, + 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETVDC, 0x46); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPANEL, 0x0b); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETCYC, 0x80); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETEQ, + 0x07, 0x07, 0x0b, 0x0b, 0x03, 0x0b, 0x00, 0x00, + 0x00, 0x00, 0xff, 0x00, 0xC0, 0x10); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPOWER, + 0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd, + 0x67, 0x77, 0x33, 0x33); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff, + 0xff, 0x01, 0xff); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETBGP, 0x09, 0x09); + mipi_dsi_msleep(dsi_ctx, 20); + + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETVCOM, 0x87, 0x95); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETGIP1, + 0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12, + 0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18, + 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x01, 0x00, 0x00, 0x00, 0x48, 0xf8, 0x86, 0x42, + 0x08, 0x88, 0x88, 0x80, 0x88, 0x88, 0x88, 0x58, + 0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88, + 0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETGIP2, + 0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35, + 0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f, + 0x88, 0x80, 0x24, 0x68, 0x88, 0x88, 0x84, 0x88, + 0x88, 0x88, 0x23, 0x10, 0x00, 0x00, 0x1c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05, + 0xa0, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETGAMMA, + 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36, + 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11, + 0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, + 0x36, 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, + 0x11, 0x18); + + mipi_dsi_msleep(dsi_ctx, 60); } static int xpp055c272_unprepare(struct drm_panel *panel) { struct xpp055c272 *ctx = panel_to_xpp055c272(panel); struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) - dev_err(ctx->dev, "failed to set display off: %d\n", ret); - - mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(ctx->dev, "failed to enter sleep mode: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + if (dsi_ctx.accum_err) + return dsi_ctx.accum_err; regulator_disable(ctx->iovcc); regulator_disable(ctx->vci); @@ -155,17 +144,19 @@ static int xpp055c272_prepare(struct drm_panel *panel) { struct xpp055c272 *ctx = panel_to_xpp055c272(panel); struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dev_dbg(ctx->dev, "Resetting the panel\n"); - ret = regulator_enable(ctx->vci); - if (ret < 0) { - dev_err(ctx->dev, "Failed to enable vci supply: %d\n", ret); - return ret; + dsi_ctx.accum_err = regulator_enable(ctx->vci); + if (dsi_ctx.accum_err) { + dev_err(ctx->dev, "Failed to enable vci supply: %d\n", + dsi_ctx.accum_err); + return dsi_ctx.accum_err; } - ret = regulator_enable(ctx->iovcc); - if (ret < 0) { - dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret); + dsi_ctx.accum_err = regulator_enable(ctx->iovcc); + if (dsi_ctx.accum_err) { + dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", + dsi_ctx.accum_err); goto disable_vci; } @@ -177,26 +168,17 @@ static int xpp055c272_prepare(struct drm_panel *panel) /* T8: 20ms */ msleep(20); - ret = xpp055c272_init_sequence(ctx); - if (ret < 0) { - dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret); - goto disable_iovcc; - } - - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret); - goto disable_iovcc; - } + xpp055c272_init_sequence(&dsi_ctx); + if (!dsi_ctx.accum_err) + dev_dbg(ctx->dev, "Panel init sequence done\n"); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); /* T9: 120ms */ - msleep(120); + mipi_dsi_msleep(&dsi_ctx, 120); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(ctx->dev, "Failed to set display on: %d\n", ret); + if (dsi_ctx.accum_err) goto disable_iovcc; - } msleep(50); @@ -206,7 +188,7 @@ disable_iovcc: regulator_disable(ctx->iovcc); disable_vci: regulator_disable(ctx->vci); - return ret; + return dsi_ctx.accum_err; } static const struct drm_display_mode default_mode = { |