diff options
Diffstat (limited to 'drivers/staging/vt6655')
26 files changed, 598 insertions, 717 deletions
diff --git a/drivers/staging/vt6655/baseband.c b/drivers/staging/vt6655/baseband.c index de503a316e71..44dfa5421374 100644 --- a/drivers/staging/vt6655/baseband.c +++ b/drivers/staging/vt6655/baseband.c @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: baseband.c * * Purpose: Implement functions to access baseband @@ -1916,7 +1911,7 @@ void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * byBBAddr - address of register in Baseband * Out: * pbyData - data read @@ -1927,24 +1922,24 @@ void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length, bool BBbReadEmbedded(struct vnt_private *priv, unsigned char byBBAddr, unsigned char *pbyData) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; unsigned short ww; unsigned char byValue; /* BB reg offset */ - VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr); + VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr); /* turn on REGR */ - MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR); + MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR); /* W_MAX_TIMEOUT is the timeout period */ for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { - VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue); + VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue); if (byValue & BBREGCTL_DONE) break; } /* get BB data */ - VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData); + VNSvInPortB(iobase + MAC_REG_BBREGDATA, pbyData); if (ww == W_MAX_TIMEOUT) { pr_debug(" DBG_PORT80(0x30)\n"); @@ -1958,7 +1953,7 @@ bool BBbReadEmbedded(struct vnt_private *priv, * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * byBBAddr - address of register in Baseband * byData - data to write * Out: @@ -1970,20 +1965,20 @@ bool BBbReadEmbedded(struct vnt_private *priv, bool BBbWriteEmbedded(struct vnt_private *priv, unsigned char byBBAddr, unsigned char byData) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; unsigned short ww; unsigned char byValue; /* BB reg offset */ - VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr); + VNSvOutPortB(iobase + MAC_REG_BBREGADR, byBBAddr); /* set BB data */ - VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData); + VNSvOutPortB(iobase + MAC_REG_BBREGDATA, byData); /* turn on BBREGCTL_REGW */ - MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW); + MACvRegBitsOn(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW); /* W_MAX_TIMEOUT is the timeout period */ for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { - VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue); + VNSvInPortB(iobase + MAC_REG_BBREGCTL, &byValue); if (byValue & BBREGCTL_DONE) break; } @@ -2000,7 +1995,7 @@ bool BBbWriteEmbedded(struct vnt_private *priv, * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * byRevId - Revision ID * byRFType - RF type * Out: @@ -2014,7 +2009,7 @@ bool BBbVT3253Init(struct vnt_private *priv) { bool bResult = true; int ii; - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; unsigned char byRFType = priv->byRFType; unsigned char byLocalID = priv->byLocalID; @@ -2036,8 +2031,8 @@ bool BBbVT3253Init(struct vnt_private *priv) byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]); - VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23); - MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0)); + VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23); + MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0)); } priv->abyBBVGA[0] = 0x18; priv->abyBBVGA[1] = 0x0A; @@ -2076,8 +2071,8 @@ bool BBbVT3253Init(struct vnt_private *priv) byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]); - VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23); - MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0)); + VNSvOutPortB(iobase + MAC_REG_ITRTMSET, 0x23); + MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0)); priv->abyBBVGA[0] = 0x14; priv->abyBBVGA[1] = 0x0A; @@ -2098,7 +2093,7 @@ bool BBbVT3253Init(struct vnt_private *priv) * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ - /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/ + /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/ /* Init ANT B select, * RX Config CR10 = 0x28->0x2A, @@ -2106,7 +2101,7 @@ bool BBbVT3253Init(struct vnt_private *priv) * make the ANT_A, ANT_B inverted) */ - /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/ + /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/ /* Select VC1/VC2, CR215 = 0x02->0x06 */ bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06); @@ -2154,7 +2149,7 @@ bool BBbVT3253Init(struct vnt_private *priv) priv->ldBmThreshold[2] = 0; priv->ldBmThreshold[3] = 0; /* Fix VT3226 DFC system timing issue */ - MACvSetRFLE_LatchBase(dwIoBase); + MACvSetRFLE_LatchBase(iobase); /* {{ RobertYu: 20050104 */ } else if (byRFType == RF_AIROHA7230) { for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) @@ -2162,16 +2157,15 @@ bool BBbVT3253Init(struct vnt_private *priv) byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]); - /* {{ RobertYu:20050223, request by JerryChung */ /* Init ANT B select,TX Config CR09 = 0x61->0x45, * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ - /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/ + /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/ /* Init ANT B select,RX Config CR10 = 0x28->0x2A, * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */ - /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/ + /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/ /* Select VC1/VC2, CR215 = 0x02->0x06 */ bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06); /* }} */ @@ -2259,7 +2253,7 @@ void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData) * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * Out: * none * @@ -2280,7 +2274,7 @@ BBvSoftwareReset(struct vnt_private *priv) * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * Out: * none * @@ -2302,7 +2296,7 @@ BBvPowerSaveModeON(struct vnt_private *priv) * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * Out: * none * diff --git a/drivers/staging/vt6655/baseband.h b/drivers/staging/vt6655/baseband.h index b4e8c43180ec..8a567c9155b4 100644 --- a/drivers/staging/vt6655/baseband.h +++ b/drivers/staging/vt6655/baseband.h @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: baseband.h * * Purpose: Implement functions to access baseband @@ -60,12 +55,6 @@ #define TOP_RATE_2M 0x00200000 #define TOP_RATE_1M 0x00100000 -#define BBvClearFOE(dwIoBase) \ - BBbWriteEmbedded(dwIoBase, 0xB1, 0) - -#define BBvSetFOE(dwIoBase) \ - BBbWriteEmbedded(dwIoBase, 0xB1, 0x0C) - unsigned int BBuGetFrameTime( unsigned char byPreambleType, diff --git a/drivers/staging/vt6655/card.c b/drivers/staging/vt6655/card.c index dbcea4434725..e0c92818ed70 100644 --- a/drivers/staging/vt6655/card.c +++ b/drivers/staging/vt6655/card.c @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: card.c * Purpose: Provide functions to setup NIC operation mode * Functions: @@ -36,7 +32,7 @@ * * Revision History: * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. - * 08-26-2003 Kyle Hsu: Modify the defination type of dwIoBase. + * 08-26-2003 Kyle Hsu: Modify the defination type of iobase. * 09-01-2003 Bryan YC Fan: Add vUpdateIFS(). * */ @@ -261,7 +257,7 @@ bool CARDbSetPhyParameter(struct vnt_private *priv, u8 bb_type) BBbWriteEmbedded(priv, 0x88, 0x02); bySlot = C_SLOT_LONG; bySIFS = C_SIFS_BG; - byDIFS = C_SIFS_BG + 2*C_SLOT_LONG; + byDIFS = C_SIFS_BG + 2 * C_SLOT_LONG; byCWMaxMin = 0xA5; } else { /* PK_TYPE_11GA & PK_TYPE_11GB */ MACvSetBBType(priv->PortOffset, BB_TYPE_11G); @@ -289,7 +285,7 @@ bool CARDbSetPhyParameter(struct vnt_private *priv, u8 bb_type) byDIFS = C_SIFS_BG + 2 * C_SLOT_SHORT; } else { bySlot = C_SLOT_LONG; - byDIFS = C_SIFS_BG + 2*C_SLOT_LONG; + byDIFS = C_SIFS_BG + 2 * C_SLOT_LONG; } byCWMaxMin = 0xa4; @@ -528,8 +524,11 @@ CARDvSafeResetTx( struct vnt_tx_desc *pCurrTD; /* initialize TD index */ - priv->apTailTD[0] = priv->apCurrTD[0] = &(priv->apTD0Rings[0]); - priv->apTailTD[1] = priv->apCurrTD[1] = &(priv->apTD1Rings[0]); + priv->apTailTD[0] = &(priv->apTD0Rings[0]); + priv->apCurrTD[0] = &(priv->apTD0Rings[0]); + + priv->apTailTD[1] = &(priv->apTD1Rings[0]); + priv->apCurrTD[1] = &(priv->apTD1Rings[0]); for (uu = 0; uu < TYPE_MAXTD; uu++) priv->iTDUsed[uu] = 0; @@ -938,20 +937,20 @@ u64 CARDqGetTSFOffset(unsigned char byRxRate, u64 qwTSF1, u64 qwTSF2) */ bool CARDbGetCurrentTSF(struct vnt_private *priv, u64 *pqwCurrTSF) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; unsigned short ww; unsigned char byData; - MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TSFCNTRRD); + MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TSFCNTRRD); for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { - VNSvInPortB(dwIoBase + MAC_REG_TFTCTL, &byData); + VNSvInPortB(iobase + MAC_REG_TFTCTL, &byData); if (!(byData & TFTCTL_TSFCNTRRD)) break; } if (ww == W_MAX_TIMEOUT) return false; - VNSvInPortD(dwIoBase + MAC_REG_TSFCNTR, (u32 *)pqwCurrTSF); - VNSvInPortD(dwIoBase + MAC_REG_TSFCNTR + 4, (u32 *)pqwCurrTSF + 1); + VNSvInPortD(iobase + MAC_REG_TSFCNTR, (u32 *)pqwCurrTSF); + VNSvInPortD(iobase + MAC_REG_TSFCNTR + 4, (u32 *)pqwCurrTSF + 1); return true; } @@ -989,7 +988,7 @@ u64 CARDqGetNextTBTT(u64 qwTSF, unsigned short wBeaconInterval) * * Parameters: * In: - * dwIoBase - IO Base + * iobase - IO Base * wBeaconInterval - Beacon Interval * Out: * none @@ -999,16 +998,16 @@ u64 CARDqGetNextTBTT(u64 qwTSF, unsigned short wBeaconInterval) void CARDvSetFirstNextTBTT(struct vnt_private *priv, unsigned short wBeaconInterval) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; u64 qwNextTBTT = 0; CARDbGetCurrentTSF(priv, &qwNextTBTT); /* Get Local TSF counter */ qwNextTBTT = CARDqGetNextTBTT(qwNextTBTT, wBeaconInterval); /* Set NextTBTT */ - VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT, (u32)qwNextTBTT); - VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32)); - MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); + VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwNextTBTT); + VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32)); + MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); } /* @@ -1028,12 +1027,12 @@ void CARDvSetFirstNextTBTT(struct vnt_private *priv, void CARDvUpdateNextTBTT(struct vnt_private *priv, u64 qwTSF, unsigned short wBeaconInterval) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; qwTSF = CARDqGetNextTBTT(qwTSF, wBeaconInterval); /* Set NextTBTT */ - VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT, (u32)qwTSF); - VNSvOutPortD(dwIoBase + MAC_REG_NEXTTBTT + 4, (u32)(qwTSF >> 32)); - MACvRegBitsOn(dwIoBase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); + VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwTSF); + VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwTSF >> 32)); + MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN); pr_debug("Card:Update Next TBTT[%8llx]\n", qwTSF); } diff --git a/drivers/staging/vt6655/card.h b/drivers/staging/vt6655/card.h index 0203c7fd91a2..44420b5a445f 100644 --- a/drivers/staging/vt6655/card.h +++ b/drivers/staging/vt6655/card.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: card.h * * Purpose: Provide functions to setup NIC operation mode @@ -50,7 +46,7 @@ #define CB_MAX_CHANNEL_24G 14 #define CB_MAX_CHANNEL_5G 42 -#define CB_MAX_CHANNEL (CB_MAX_CHANNEL_24G+CB_MAX_CHANNEL_5G) +#define CB_MAX_CHANNEL (CB_MAX_CHANNEL_24G + CB_MAX_CHANNEL_5G) typedef enum _CARD_PKT_TYPE { PKT_TYPE_802_11_BCN, diff --git a/drivers/staging/vt6655/channel.c b/drivers/staging/vt6655/channel.c index 029a8df4ca1c..ab89956511a0 100644 --- a/drivers/staging/vt6655/channel.c +++ b/drivers/staging/vt6655/channel.c @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: channel.c * */ diff --git a/drivers/staging/vt6655/channel.h b/drivers/staging/vt6655/channel.h index 2d613e7f169c..2621dfabff06 100644 --- a/drivers/staging/vt6655/channel.h +++ b/drivers/staging/vt6655/channel.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: channel.h * */ diff --git a/drivers/staging/vt6655/desc.h b/drivers/staging/vt6655/desc.h index 2d7f6ae89164..2fee6e759ad8 100644 --- a/drivers/staging/vt6655/desc.h +++ b/drivers/staging/vt6655/desc.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: desc.h * * Purpose:The header file of descriptor diff --git a/drivers/staging/vt6655/device.h b/drivers/staging/vt6655/device.h index 55405e058196..3ae40d846a09 100644 --- a/drivers/staging/vt6655/device.h +++ b/drivers/staging/vt6655/device.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: device.h * * Purpose: MAC Data structure @@ -283,12 +279,12 @@ struct vnt_private { unsigned char byOFDMPwrG; unsigned char byCurPwr; char byCurPwrdBm; - unsigned char abyCCKPwrTbl[CB_MAX_CHANNEL_24G+1]; - unsigned char abyOFDMPwrTbl[CB_MAX_CHANNEL+1]; - char abyCCKDefaultPwr[CB_MAX_CHANNEL_24G+1]; - char abyOFDMDefaultPwr[CB_MAX_CHANNEL+1]; - char abyRegPwr[CB_MAX_CHANNEL+1]; - char abyLocalPwr[CB_MAX_CHANNEL+1]; + unsigned char abyCCKPwrTbl[CB_MAX_CHANNEL_24G + 1]; + unsigned char abyOFDMPwrTbl[CB_MAX_CHANNEL + 1]; + char abyCCKDefaultPwr[CB_MAX_CHANNEL_24G + 1]; + char abyOFDMDefaultPwr[CB_MAX_CHANNEL + 1]; + char abyRegPwr[CB_MAX_CHANNEL + 1]; + char abyLocalPwr[CB_MAX_CHANNEL + 1]; /* BaseBand Loopback Use */ unsigned char byBBCR4d; diff --git a/drivers/staging/vt6655/device_cfg.h b/drivers/staging/vt6655/device_cfg.h index b4c9547d3138..0298ea923f97 100644 --- a/drivers/staging/vt6655/device_cfg.h +++ b/drivers/staging/vt6655/device_cfg.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: device_cfg.h * * Purpose: Driver configuration header diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c index f109eeac358d..da0f71191009 100644 --- a/drivers/staging/vt6655/device_main.c +++ b/drivers/staging/vt6655/device_main.c @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: device_main.c * * Purpose: driver entry for initial, open, close, tx and rx. @@ -314,7 +310,7 @@ static void device_init_registers(struct vnt_private *priv) SROMbyReadEmbedded(priv->PortOffset, (unsigned char)(ii + EEP_OFS_CCK_PWR_TBL)); if (priv->abyCCKPwrTbl[ii + 1] == 0) - priv->abyCCKPwrTbl[ii+1] = priv->byCCKPwr; + priv->abyCCKPwrTbl[ii + 1] = priv->byCCKPwr; priv->abyOFDMPwrTbl[ii + 1] = SROMbyReadEmbedded(priv->PortOffset, @@ -556,7 +552,7 @@ static void device_init_rd0_ring(struct vnt_private *priv) if (!device_alloc_rx_buf(priv, desc)) dev_err(&priv->pcid->dev, "can not alloc rx bufs\n"); - desc->next = &(priv->aRD0Ring[(i+1) % priv->opts.rx_descs0]); + desc->next = &(priv->aRD0Ring[(i + 1) % priv->opts.rx_descs0]); desc->next_desc = cpu_to_le32(curr + sizeof(struct vnt_rx_desc)); } @@ -1272,7 +1268,6 @@ static void vnt_remove_interface(struct ieee80211_hw *hw, priv->op_mode = NL80211_IFTYPE_UNSPECIFIED; } - static int vnt_config(struct ieee80211_hw *hw, u32 changed) { struct vnt_private *priv = hw->priv; diff --git a/drivers/staging/vt6655/dpc.c b/drivers/staging/vt6655/dpc.c index 700032e9c477..9b3fa779258a 100644 --- a/drivers/staging/vt6655/dpc.c +++ b/drivers/staging/vt6655/dpc.c @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: dpc.c * * Purpose: handle dpc rx functions diff --git a/drivers/staging/vt6655/dpc.h b/drivers/staging/vt6655/dpc.h index e80b30816968..6e75fa9c5618 100644 --- a/drivers/staging/vt6655/dpc.h +++ b/drivers/staging/vt6655/dpc.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: dpc.h * * Purpose: diff --git a/drivers/staging/vt6655/key.c b/drivers/staging/vt6655/key.c index e161d5d9aebb..dad9e292d4da 100644 --- a/drivers/staging/vt6655/key.c +++ b/drivers/staging/vt6655/key.c @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: key.c * * Purpose: Implement functions for 802.11i Key management diff --git a/drivers/staging/vt6655/key.h b/drivers/staging/vt6655/key.h index d72719741a56..a5024611af60 100644 --- a/drivers/staging/vt6655/key.h +++ b/drivers/staging/vt6655/key.h @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: key.h * * Purpose: Implement functions for 802.11i Key management diff --git a/drivers/staging/vt6655/mac.c b/drivers/staging/vt6655/mac.c index 8e13f7f41415..4aaa99bafcda 100644 --- a/drivers/staging/vt6655/mac.c +++ b/drivers/staging/vt6655/mac.c @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: mac.c * * Purpose: MAC routines @@ -147,7 +142,6 @@ void MACvSetShortRetryLimit(struct vnt_private *priv, iowrite8(byRetryLimit, io_base + MAC_REG_SRT); } - /* * Description: * Set 802.11 Long Retry Limit @@ -321,7 +315,7 @@ bool MACbSoftwareReset(struct vnt_private *priv) */ bool MACbSafeSoftwareReset(struct vnt_private *priv) { - unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0+MAC_MAX_CONTEXT_SIZE_PAGE1]; + unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1]; bool bRetVal; /* PATCH.... diff --git a/drivers/staging/vt6655/mac.h b/drivers/staging/vt6655/mac.h index 030f529c339b..33b758cb79d4 100644 --- a/drivers/staging/vt6655/mac.h +++ b/drivers/staging/vt6655/mac.h @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: mac.h * * Purpose: MAC routines @@ -554,341 +549,341 @@ /*--------------------- Export Macros ------------------------------*/ -#define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \ +#define MACvRegBitsOn(iobase, byRegOfs, byBits) \ do { \ unsigned char byData; \ - VNSvInPortB(dwIoBase + byRegOfs, &byData); \ - VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \ + VNSvInPortB(iobase + byRegOfs, &byData); \ + VNSvOutPortB(iobase + byRegOfs, byData | (byBits)); \ } while (0) -#define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \ +#define MACvWordRegBitsOn(iobase, byRegOfs, wBits) \ do { \ unsigned short wData; \ - VNSvInPortW(dwIoBase + byRegOfs, &wData); \ - VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \ + VNSvInPortW(iobase + byRegOfs, &wData); \ + VNSvOutPortW(iobase + byRegOfs, wData | (wBits)); \ } while (0) -#define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \ +#define MACvDWordRegBitsOn(iobase, byRegOfs, dwBits) \ do { \ unsigned long dwData; \ - VNSvInPortD(dwIoBase + byRegOfs, &dwData); \ - VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \ + VNSvInPortD(iobase + byRegOfs, &dwData); \ + VNSvOutPortD(iobase + byRegOfs, dwData | (dwBits)); \ } while (0) -#define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \ +#define MACvRegBitsOnEx(iobase, byRegOfs, byMask, byBits) \ do { \ unsigned char byData; \ - VNSvInPortB(dwIoBase + byRegOfs, &byData); \ + VNSvInPortB(iobase + byRegOfs, &byData); \ byData &= byMask; \ - VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \ + VNSvOutPortB(iobase + byRegOfs, byData | (byBits)); \ } while (0) -#define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \ +#define MACvRegBitsOff(iobase, byRegOfs, byBits) \ do { \ unsigned char byData; \ - VNSvInPortB(dwIoBase + byRegOfs, &byData); \ - VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \ + VNSvInPortB(iobase + byRegOfs, &byData); \ + VNSvOutPortB(iobase + byRegOfs, byData & ~(byBits)); \ } while (0) -#define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \ +#define MACvWordRegBitsOff(iobase, byRegOfs, wBits) \ do { \ unsigned short wData; \ - VNSvInPortW(dwIoBase + byRegOfs, &wData); \ - VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \ + VNSvInPortW(iobase + byRegOfs, &wData); \ + VNSvOutPortW(iobase + byRegOfs, wData & ~(wBits)); \ } while (0) -#define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \ +#define MACvDWordRegBitsOff(iobase, byRegOfs, dwBits) \ do { \ unsigned long dwData; \ - VNSvInPortD(dwIoBase + byRegOfs, &dwData); \ - VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \ + VNSvInPortD(iobase + byRegOfs, &dwData); \ + VNSvOutPortD(iobase + byRegOfs, dwData & ~(dwBits)); \ } while (0) -#define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \ - VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \ +#define MACvGetCurrRx0DescAddr(iobase, pdwCurrDescAddr) \ + VNSvInPortD(iobase + MAC_REG_RXDMAPTR0, \ (unsigned long *)pdwCurrDescAddr) -#define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \ - VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \ +#define MACvGetCurrRx1DescAddr(iobase, pdwCurrDescAddr) \ + VNSvInPortD(iobase + MAC_REG_RXDMAPTR1, \ (unsigned long *)pdwCurrDescAddr) -#define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \ - VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \ +#define MACvGetCurrTx0DescAddr(iobase, pdwCurrDescAddr) \ + VNSvInPortD(iobase + MAC_REG_TXDMAPTR0, \ (unsigned long *)pdwCurrDescAddr) -#define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \ - VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \ +#define MACvGetCurrAC0DescAddr(iobase, pdwCurrDescAddr) \ + VNSvInPortD(iobase + MAC_REG_AC0DMAPTR, \ (unsigned long *)pdwCurrDescAddr) -#define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \ - VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \ +#define MACvGetCurrSyncDescAddr(iobase, pdwCurrDescAddr) \ + VNSvInPortD(iobase + MAC_REG_SYNCDMAPTR, \ (unsigned long *)pdwCurrDescAddr) -#define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \ - VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \ +#define MACvGetCurrATIMDescAddr(iobase, pdwCurrDescAddr) \ + VNSvInPortD(iobase + MAC_REG_ATIMDMAPTR, \ (unsigned long *)pdwCurrDescAddr) /* set the chip with current BCN tx descriptor address */ -#define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \ - VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \ +#define MACvSetCurrBCNTxDescAddr(iobase, dwCurrDescAddr) \ + VNSvOutPortD(iobase + MAC_REG_BCNDMAPTR, \ dwCurrDescAddr) /* set the chip with current BCN length */ -#define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \ - VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \ +#define MACvSetCurrBCNLength(iobase, wCurrBCNLength) \ + VNSvOutPortW(iobase + MAC_REG_BCNDMACTL+2, \ wCurrBCNLength) -#define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \ +#define MACvReadBSSIDAddress(iobase, pbyEtherAddr) \ do { \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ - VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \ + VNSvInPortB(iobase + MAC_REG_BSSID0, \ (unsigned char *)pbyEtherAddr); \ - VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \ + VNSvInPortB(iobase + MAC_REG_BSSID0 + 1, \ pbyEtherAddr + 1); \ - VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \ + VNSvInPortB(iobase + MAC_REG_BSSID0 + 2, \ pbyEtherAddr + 2); \ - VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \ + VNSvInPortB(iobase + MAC_REG_BSSID0 + 3, \ pbyEtherAddr + 3); \ - VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \ + VNSvInPortB(iobase + MAC_REG_BSSID0 + 4, \ pbyEtherAddr + 4); \ - VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \ + VNSvInPortB(iobase + MAC_REG_BSSID0 + 5, \ pbyEtherAddr + 5); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \ } while (0) -#define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \ +#define MACvWriteBSSIDAddress(iobase, pbyEtherAddr) \ do { \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ - VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \ + VNSvOutPortB(iobase + MAC_REG_BSSID0, \ *(pbyEtherAddr)); \ - VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \ + VNSvOutPortB(iobase + MAC_REG_BSSID0 + 1, \ *(pbyEtherAddr + 1)); \ - VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \ + VNSvOutPortB(iobase + MAC_REG_BSSID0 + 2, \ *(pbyEtherAddr + 2)); \ - VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \ + VNSvOutPortB(iobase + MAC_REG_BSSID0 + 3, \ *(pbyEtherAddr + 3)); \ - VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \ + VNSvOutPortB(iobase + MAC_REG_BSSID0 + 4, \ *(pbyEtherAddr + 4)); \ - VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \ + VNSvOutPortB(iobase + MAC_REG_BSSID0 + 5, \ *(pbyEtherAddr + 5)); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \ } while (0) -#define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \ +#define MACvReadEtherAddress(iobase, pbyEtherAddr) \ do { \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ - VNSvInPortB(dwIoBase + MAC_REG_PAR0, \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \ + VNSvInPortB(iobase + MAC_REG_PAR0, \ (unsigned char *)pbyEtherAddr); \ - VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \ + VNSvInPortB(iobase + MAC_REG_PAR0 + 1, \ pbyEtherAddr + 1); \ - VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \ + VNSvInPortB(iobase + MAC_REG_PAR0 + 2, \ pbyEtherAddr + 2); \ - VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \ + VNSvInPortB(iobase + MAC_REG_PAR0 + 3, \ pbyEtherAddr + 3); \ - VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \ + VNSvInPortB(iobase + MAC_REG_PAR0 + 4, \ pbyEtherAddr + 4); \ - VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \ + VNSvInPortB(iobase + MAC_REG_PAR0 + 5, \ pbyEtherAddr + 5); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \ } while (0) -#define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \ +#define MACvWriteEtherAddress(iobase, pbyEtherAddr) \ do { \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \ + VNSvOutPortB(iobase + MAC_REG_PAR0, \ *pbyEtherAddr); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \ + VNSvOutPortB(iobase + MAC_REG_PAR0 + 1, \ *(pbyEtherAddr + 1)); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \ + VNSvOutPortB(iobase + MAC_REG_PAR0 + 2, \ *(pbyEtherAddr + 2)); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \ + VNSvOutPortB(iobase + MAC_REG_PAR0 + 3, \ *(pbyEtherAddr + 3)); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \ + VNSvOutPortB(iobase + MAC_REG_PAR0 + 4, \ *(pbyEtherAddr + 4)); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \ + VNSvOutPortB(iobase + MAC_REG_PAR0 + 5, \ *(pbyEtherAddr + 5)); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \ } while (0) -#define MACvClearISR(dwIoBase) \ - VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE) +#define MACvClearISR(iobase) \ + VNSvOutPortD(iobase + MAC_REG_ISR, IMR_MASK_VALUE) -#define MACvStart(dwIoBase) \ - VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \ +#define MACvStart(iobase) \ + VNSvOutPortB(iobase + MAC_REG_HOSTCR, \ (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)) -#define MACvRx0PerPktMode(dwIoBase) \ - VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT) +#define MACvRx0PerPktMode(iobase) \ + VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKT) -#define MACvRx0BufferFillMode(dwIoBase) \ - VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR) +#define MACvRx0BufferFillMode(iobase) \ + VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKTCLR) -#define MACvRx1PerPktMode(dwIoBase) \ - VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT) +#define MACvRx1PerPktMode(iobase) \ + VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKT) -#define MACvRx1BufferFillMode(dwIoBase) \ - VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR) +#define MACvRx1BufferFillMode(iobase) \ + VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKTCLR) -#define MACvRxOn(dwIoBase) \ - MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON) +#define MACvRxOn(iobase) \ + MACvRegBitsOn(iobase, MAC_REG_HOSTCR, HOSTCR_RXON) -#define MACvReceive0(dwIoBase) \ +#define MACvReceive0(iobase) \ do { \ unsigned long dwData; \ - VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \ + VNSvInPortD(iobase + MAC_REG_RXDMACTL0, &dwData); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \ + VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \ else \ - VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \ + VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_RUN); \ } while (0) -#define MACvReceive1(dwIoBase) \ +#define MACvReceive1(iobase) \ do { \ unsigned long dwData; \ - VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \ + VNSvInPortD(iobase + MAC_REG_RXDMACTL1, &dwData); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \ + VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \ else \ - VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \ + VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_RUN); \ } while (0) -#define MACvTxOn(dwIoBase) \ - MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON) +#define MACvTxOn(iobase) \ + MACvRegBitsOn(iobase, MAC_REG_HOSTCR, HOSTCR_TXON) -#define MACvTransmit0(dwIoBase) \ +#define MACvTransmit0(iobase) \ do { \ unsigned long dwData; \ - VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \ + VNSvInPortD(iobase + MAC_REG_TXDMACTL0, &dwData); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \ + VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \ else \ - VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \ + VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_RUN); \ } while (0) -#define MACvTransmitAC0(dwIoBase) \ +#define MACvTransmitAC0(iobase) \ do { \ unsigned long dwData; \ - VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \ + VNSvInPortD(iobase + MAC_REG_AC0DMACTL, &dwData); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \ + VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \ else \ - VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \ + VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_RUN); \ } while (0) -#define MACvTransmitSYNC(dwIoBase) \ +#define MACvTransmitSYNC(iobase) \ do { \ unsigned long dwData; \ - VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \ + VNSvInPortD(iobase + MAC_REG_SYNCDMACTL, &dwData); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \ + VNSvOutPortD(iobase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \ else \ - VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \ + VNSvOutPortD(iobase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \ } while (0) -#define MACvTransmitATIM(dwIoBase) \ +#define MACvTransmitATIM(iobase) \ do { \ unsigned long dwData; \ - VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \ + VNSvInPortD(iobase + MAC_REG_ATIMDMACTL, &dwData); \ if (dwData & DMACTL_RUN) \ - VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \ + VNSvOutPortD(iobase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \ else \ - VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \ + VNSvOutPortD(iobase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \ } while (0) -#define MACvTransmitBCN(dwIoBase) \ - VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY) +#define MACvTransmitBCN(iobase) \ + VNSvOutPortB(iobase + MAC_REG_BCNDMACTL, BEACON_READY) -#define MACvClearStckDS(dwIoBase) \ +#define MACvClearStckDS(iobase) \ do { \ unsigned char byOrgValue; \ - VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \ + VNSvInPortB(iobase + MAC_REG_STICKHW, &byOrgValue); \ byOrgValue = byOrgValue & 0xFC; \ - VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \ + VNSvOutPortB(iobase + MAC_REG_STICKHW, byOrgValue); \ } while (0) -#define MACvReadISR(dwIoBase, pdwValue) \ - VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue) +#define MACvReadISR(iobase, pdwValue) \ + VNSvInPortD(iobase + MAC_REG_ISR, pdwValue) -#define MACvWriteISR(dwIoBase, dwValue) \ - VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue) +#define MACvWriteISR(iobase, dwValue) \ + VNSvOutPortD(iobase + MAC_REG_ISR, dwValue) -#define MACvIntEnable(dwIoBase, dwMask) \ - VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask) +#define MACvIntEnable(iobase, dwMask) \ + VNSvOutPortD(iobase + MAC_REG_IMR, dwMask) -#define MACvIntDisable(dwIoBase) \ - VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0) +#define MACvIntDisable(iobase) \ + VNSvOutPortD(iobase + MAC_REG_IMR, 0) -#define MACvSelectPage0(dwIoBase) \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0) +#define MACvSelectPage0(iobase) \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0) -#define MACvSelectPage1(dwIoBase) \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1) +#define MACvSelectPage1(iobase) \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1) -#define MACvReadMIBCounter(dwIoBase, pdwCounter) \ - VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR, pdwCounter) +#define MACvReadMIBCounter(iobase, pdwCounter) \ + VNSvInPortD(iobase + MAC_REG_MIBCNTR, pdwCounter) -#define MACvPwrEvntDisable(dwIoBase) \ - VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000) +#define MACvPwrEvntDisable(iobase) \ + VNSvOutPortW(iobase + MAC_REG_WAKEUPEN0, 0x0000) -#define MACvEnableProtectMD(dwIoBase) \ +#define MACvEnableProtectMD(iobase) \ do { \ unsigned long dwOrgValue; \ - VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \ dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \ - VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ + VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ } while (0) -#define MACvDisableProtectMD(dwIoBase) \ +#define MACvDisableProtectMD(iobase) \ do { \ unsigned long dwOrgValue; \ - VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \ dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \ - VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ + VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ } while (0) -#define MACvEnableBarkerPreambleMd(dwIoBase) \ +#define MACvEnableBarkerPreambleMd(iobase) \ do { \ unsigned long dwOrgValue; \ - VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \ dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \ - VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ + VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ } while (0) -#define MACvDisableBarkerPreambleMd(dwIoBase) \ +#define MACvDisableBarkerPreambleMd(iobase) \ do { \ unsigned long dwOrgValue; \ - VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \ dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \ - VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ + VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ } while (0) -#define MACvSetBBType(dwIoBase, byTyp) \ +#define MACvSetBBType(iobase, byTyp) \ do { \ unsigned long dwOrgValue; \ - VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ + VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \ dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \ dwOrgValue = dwOrgValue | (unsigned long)byTyp; \ - VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ + VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \ } while (0) -#define MACvReadATIMW(dwIoBase, pwCounter) \ - VNSvInPortW(dwIoBase + MAC_REG_AIDATIM, pwCounter) +#define MACvReadATIMW(iobase, pwCounter) \ + VNSvInPortW(iobase + MAC_REG_AIDATIM, pwCounter) -#define MACvWriteATIMW(dwIoBase, wCounter) \ - VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM, wCounter) +#define MACvWriteATIMW(iobase, wCounter) \ + VNSvOutPortW(iobase + MAC_REG_AIDATIM, wCounter) -#define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \ +#define MACvWriteCRC16_128(iobase, byRegOfs, wCRC) \ do { \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ - VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \ - VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \ + VNSvOutPortW(iobase + byRegOfs, wCRC); \ + VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \ } while (0) -#define MACvGPIOIn(dwIoBase, pbyValue) \ - VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue) +#define MACvGPIOIn(iobase, pbyValue) \ + VNSvInPortB(iobase + MAC_REG_GPIOCTL1, pbyValue) -#define MACvSetRFLE_LatchBase(dwIoBase) \ - MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT) +#define MACvSetRFLE_LatchBase(iobase) \ + MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT) bool MACbIsRegBitsOn(struct vnt_private *, unsigned char byRegOfs, unsigned char byTestBits); diff --git a/drivers/staging/vt6655/power.c b/drivers/staging/vt6655/power.c index 7d6e7464ae51..716d2a80f840 100644 --- a/drivers/staging/vt6655/power.c +++ b/drivers/staging/vt6655/power.c @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: power.c * * Purpose: Handles 802.11 power management functions @@ -133,7 +128,6 @@ PSvDisablePowerSaving( priv->bPWBitOn = false; } - /* * * Routine Description: diff --git a/drivers/staging/vt6655/power.h b/drivers/staging/vt6655/power.h index d82dd8d6d68b..dfcb0ca8b448 100644 --- a/drivers/staging/vt6655/power.h +++ b/drivers/staging/vt6655/power.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: power.h * * Purpose: Handles 802.11 power management functions @@ -46,7 +42,6 @@ PSvEnablePowerSaving( unsigned short wListenInterval ); - bool PSbIsNextTBTTWakeUp( struct vnt_private * diff --git a/drivers/staging/vt6655/rf.c b/drivers/staging/vt6655/rf.c index 447882c7a6be..edf7db9d53b3 100644 --- a/drivers/staging/vt6655/rf.c +++ b/drivers/staging/vt6655/rf.c @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: rf.c * * Purpose: rf function code @@ -50,359 +45,362 @@ #define AL7230_PWR_IDX_LEN 64 static const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = { - 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW + 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x00068800 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0403B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x00DBBA00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0BDFFC00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x00000D00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x00580F00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW }; static const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = { - 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ - 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ - 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ - 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ - 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ - 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ - 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ - 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ - 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ - 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ - 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ - 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ - 0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ - 0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW /* channel = 14, Tf = 2412M */ + 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ + 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ + 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ + 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ + 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ + 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ + 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ + 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ + 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ + 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ + 0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ + 0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ + 0x03F7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ + 0x03E7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 14, Tf = 2412M */ }; static const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = { - 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ - 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ - 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ - 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ - 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ - 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ - 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ - 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ - 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ - 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ - 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ - 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ - 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ - 0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW /* channel = 14, Tf = 2412M */ + 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ + 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ + 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ + 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ + 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ + 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ + 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ + 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ + 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ + 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ + 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ + 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ + 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ + 0x06666100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 14, Tf = 2412M */ }; static unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = { - 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, - 0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW + 0x04040900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04041900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04042900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04043900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04044900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04045900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04046900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04047900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04048900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04049900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0404A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0404B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0404C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0404D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0404E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0404F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04050900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04051900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04052900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04053900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04054900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04055900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04056900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04057900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04058900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04059900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0405A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0405B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0405C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0405D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0405E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0405F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04060900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04061900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04062900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04063900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04064900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04065900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04066900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04067900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04068900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04069900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0406A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0406B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0406C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0406D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0406E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0406F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04070900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04071900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04072900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04073900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04074900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04075900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04076900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04077900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04078900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x04079900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0407A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0407B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0407C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0407D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0407E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, + 0x0407F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW }; /* 40MHz reference frequency * Need to Pull PLLON(PE3) low when writing channel registers through 3-wire. */ static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = { - 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Channel1 // Need modify for 11a */ - 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Channel1 // Need modify for 11a */ - 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11a: 451FE2 */ - 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11a: 5FDFA3 */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* 11b/g // Need modify for 11a */ + 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel1 // Need modify for 11a */ + 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel1 // Need modify for 11a */ + 0x841FF200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 451FE2 */ + 0x3FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 5FDFA3 */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11b/g // Need modify for 11a */ /* RoberYu:20050113, Rev0.47 Regsiter Setting Guide */ - 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11a: 8D1B55 */ - 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11a: 860207 */ - 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11a: E0600A */ - 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */ + 0x802B5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 8D1B55 */ + 0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 860207 */ + 0x6EBC0800 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0xE0000A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: E0600A */ + 0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */ /* RoberYu:20050113, Rev0.47 Regsiter Setting Guide */ - 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11a: 00143C */ - 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW /* Need modify for 11a: 12BACF */ + 0x000A3C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 00143C */ + 0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0x1ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* Need modify for 11a: 12BACF */ }; static const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = { - 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */ - 0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11b/g */ - 0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11b/g */ - 0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* 11a // Need modify for 11b/g */ - 0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11b/g, RoberYu:20050113 */ - 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11b/g */ - 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11b/g */ - 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */ - 0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* Need modify for 11b/g */ - 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, - 0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW /* Need modify for 11b/g */ + 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */ + 0x451FE200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ + 0x5FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ + 0x67F78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11a // Need modify for 11b/g */ + 0x853F5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g, RoberYu:20050113 */ + 0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ + 0x6EBC0800 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0xE0600A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ + 0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */ + 0x00147C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ + 0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, + 0x12BACF00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* Need modify for 11b/g */ }; static const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = { - 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ - 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ - 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ - 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ - 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ - 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ - 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ - 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 */ - 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 */ - 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 */ - 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 */ - 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 */ - 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 */ - 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ + 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ + 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ + 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ + 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ + 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ + 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ + 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ + 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 */ + 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 */ + 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 */ + 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 */ + 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 */ + 0x0037C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 */ + 0x0037C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */ - 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ - 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ - 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ - 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ - 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ - 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ - 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ - 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ + 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ + 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ + 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ + 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ + 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ + 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ + 0x0FF53000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ + 0x0FF53000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, - * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) */ - - 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ - 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ - 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ - 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ - 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ - 0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ - 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ - 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ - 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 */ - 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ - 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ - 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ - 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ - 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ - 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ - 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ - 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ - 0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ - - 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ - 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ - 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ - 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ - 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ - 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ - 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ - 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ - 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ - 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ - 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ - 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ - 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ - 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ - 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ - 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ + * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) + */ + + 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ + 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ + 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ + 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ + 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ + 0x0FF55000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ + 0x0FF56000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ + 0x0FF56000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ + 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 */ + 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ + 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ + 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ + 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ + 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ + 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ + 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ + 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ + 0x0FF59000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ + + 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ + 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ + 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ + 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ + 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ + 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ + 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ + 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ + 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ + 0x0FF5F000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ + 0x0FF5F000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ + 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ + 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ + 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ + 0x0FF61000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ + 0x0FF61000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ }; static const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = { - 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ - 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ - 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ - 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ - 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ - 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ - 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ - 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ - 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ - 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ - 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ - 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ - 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ - 0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ + 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ + 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ + 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ + 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ + 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ + 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ + 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ + 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ + 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ + 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ + 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ + 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ + 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ + 0x06666100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */ - 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ - 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ - 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ - 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ - 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ + 0x1D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ + 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ + 0x08000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ + 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ + 0x0D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, - * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) */ - 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ - 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ - 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ - 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ - 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ - 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ - 0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ - 0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ - 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ - 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ - 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ - 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ - 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ - 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ - 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ - 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ - 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ - 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ - 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ - 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ - 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ + * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) + */ + 0x1D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ + 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ + 0x08000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ + 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ + 0x05555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ + 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ + 0x10000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ + 0x1AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ + 0x05555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ + 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ + 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ + 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ + 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ + 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ + 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ + 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ + 0x18000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ + 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ + 0x0D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ + 0x18000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ + 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ }; static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ - 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ + 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, - * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ - 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ - 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ + * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) + */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ + 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ + 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ }; /* @@ -410,7 +408,7 @@ static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * Out: * none * @@ -419,16 +417,16 @@ static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { */ static bool s_bAL7230Init(struct vnt_private *priv) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; int ii; bool ret; ret = true; /* 3-wire control for normal mode */ - VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); + VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0); - MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | + MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); BBvPowerSaveModeOFF(priv); /* RobertYu:20050106, have DC value for Calibration */ @@ -436,20 +434,20 @@ static bool s_bAL7230Init(struct vnt_private *priv) ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[ii]); /* PLL On */ - MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); /* Calibration */ MACvTimer0MicroSDelay(priv, 150);/* 150us */ /* TXDCOC:active, RCK:disable */ - ret &= IFRFbWriteEmbedded(priv, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); + ret &= IFRFbWriteEmbedded(priv, (0x9ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW)); MACvTimer0MicroSDelay(priv, 30);/* 30us */ /* TXDCOC:disable, RCK:active */ - ret &= IFRFbWriteEmbedded(priv, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); + ret &= IFRFbWriteEmbedded(priv, (0x3ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW)); MACvTimer0MicroSDelay(priv, 30);/* 30us */ /* TXDCOC:disable, RCK:disable */ ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); - MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | + MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | SOFTPWRCTL_SWPE2 | SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); @@ -458,7 +456,7 @@ static bool s_bAL7230Init(struct vnt_private *priv) /* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */ /* 3-wire control for power saving mode */ - VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */ + VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */ return ret; } @@ -468,26 +466,26 @@ static bool s_bAL7230Init(struct vnt_private *priv) */ static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byChannel) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; bool ret; ret = true; /* PLLON Off */ - MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable0[byChannel - 1]); ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable1[byChannel - 1]); ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable2[byChannel - 1]); /* PLLOn On */ - MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); /* Set Channel[7] = 0 to tell H/W channel is changing now. */ - VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); + VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F)); MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL7230); /* Set Channel[7] = 1 to tell H/W channel change is done. */ - VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); + VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80)); return ret; } @@ -497,7 +495,7 @@ static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byCha * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * dwData - data to write * Out: * none @@ -507,15 +505,15 @@ static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byCha */ bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; unsigned short ww; unsigned long dwValue; - VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData); + VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData); /* W_MAX_TIMEOUT is the timeout period */ for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { - VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue); + VNSvInPortD(iobase + MAC_REG_IFREGCTL, &dwValue); if (dwValue & IFREGCTL_DONE) break; } @@ -531,7 +529,7 @@ bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * Out: * none * @@ -540,51 +538,51 @@ bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) */ static bool RFbAL2230Init(struct vnt_private *priv) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; int ii; bool ret; ret = true; /* 3-wire control for normal mode */ - VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); + VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0); - MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | + MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); /* PLL Off */ - MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); /* patch abnormal AL2230 frequency output */ - IFRFbWriteEmbedded(priv, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); + IFRFbWriteEmbedded(priv, (0x07168700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW)); for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) ret &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[ii]); MACvTimer0MicroSDelay(priv, 30); /* delay 30 us */ /* PLL On */ - MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); + MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); MACvTimer0MicroSDelay(priv, 150);/* 150us */ - ret &= IFRFbWriteEmbedded(priv, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); + ret &= IFRFbWriteEmbedded(priv, (0x00d80f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW)); MACvTimer0MicroSDelay(priv, 30);/* 30us */ - ret &= IFRFbWriteEmbedded(priv, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); + ret &= IFRFbWriteEmbedded(priv, (0x00780f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW)); MACvTimer0MicroSDelay(priv, 30);/* 30us */ ret &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]); - MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | + MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | SOFTPWRCTL_SWPE2 | SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV)); /* 3-wire control for power saving mode */ - VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */ + VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */ return ret; } static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; bool ret; ret = true; @@ -593,10 +591,10 @@ static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byCha ret &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable1[byChannel - 1]); /* Set Channel[7] = 0 to tell H/W channel is changing now. */ - VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); + VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F)); MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL2230); /* Set Channel[7] = 1 to tell H/W channel change is done. */ - VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); + VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80)); return ret; } @@ -681,7 +679,7 @@ bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType, * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * uChannel - channel number * bySleepCnt - SleepProgSyn count * @@ -691,12 +689,12 @@ bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType, bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType, u16 uChannel) { - void __iomem *dwIoBase = priv->PortOffset; + void __iomem *iobase = priv->PortOffset; int ii; unsigned char byInitCount = 0; unsigned char bySleepCount = 0; - VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0); + VNSvOutPortW(iobase + MAC_REG_MISCFFNDEX, 0); switch (byRFType) { case RF_AIROHA: case RF_AL2230S: @@ -758,7 +756,7 @@ bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType, * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * dwRFPowerTable - RF Tx Power Setting * Out: * none @@ -830,7 +828,7 @@ bool RFbSetPower( * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * dwRFPowerTable - RF Tx Power Setting * Out: * none @@ -855,20 +853,20 @@ bool RFbRawSetPower( case RF_AIROHA: ret &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]); if (rate <= RATE_11M) - ret &= IFRFbWriteEmbedded(priv, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + ret &= IFRFbWriteEmbedded(priv, 0x0001B400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); else - ret &= IFRFbWriteEmbedded(priv, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); break; case RF_AL2230S: ret &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]); if (rate <= RATE_11M) { - ret &= IFRFbWriteEmbedded(priv, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); - ret &= IFRFbWriteEmbedded(priv, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + ret &= IFRFbWriteEmbedded(priv, 0x040C1400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); + ret &= IFRFbWriteEmbedded(priv, 0x00299B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); } else { - ret &= IFRFbWriteEmbedded(priv, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); - ret &= IFRFbWriteEmbedded(priv, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); + ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); + ret &= IFRFbWriteEmbedded(priv, 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); } break; diff --git a/drivers/staging/vt6655/rf.h b/drivers/staging/vt6655/rf.h index e9c786995506..b6e853784a26 100644 --- a/drivers/staging/vt6655/rf.h +++ b/drivers/staging/vt6655/rf.h @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: rf.h * * Purpose: diff --git a/drivers/staging/vt6655/rxtx.c b/drivers/staging/vt6655/rxtx.c index 7e69bc99d60f..3efe19a1b13f 100644 --- a/drivers/staging/vt6655/rxtx.c +++ b/drivers/staging/vt6655/rxtx.c @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: rxtx.c * * Purpose: handle WMAC/802.3/802.11 rx & tx functions @@ -1086,8 +1082,8 @@ s_cbFillTxBufHead(struct vnt_private *pDevice, unsigned char byPktType, } /* - * Use for AUTO FALL BACK - */ + * Use for AUTO FALL BACK + */ if (fifo_ctl & FIFOCTL_AUTO_FB_0) byFBOption = AUTO_FB_0; else if (fifo_ctl & FIFOCTL_AUTO_FB_1) diff --git a/drivers/staging/vt6655/rxtx.h b/drivers/staging/vt6655/rxtx.h index 1e30ecb5c63c..89de67115826 100644 --- a/drivers/staging/vt6655/rxtx.h +++ b/drivers/staging/vt6655/rxtx.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: rxtx.h * * Purpose: diff --git a/drivers/staging/vt6655/srom.c b/drivers/staging/vt6655/srom.c index ee992772066f..635f271595f6 100644 --- a/drivers/staging/vt6655/srom.c +++ b/drivers/staging/vt6655/srom.c @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: srom.c * * Purpose:Implement functions to access eeprom @@ -64,7 +60,7 @@ * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * byContntOffset - address of EEPROM * Out: * none @@ -72,7 +68,7 @@ * Return Value: data read * */ -unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, +unsigned char SROMbyReadEmbedded(void __iomem *iobase, unsigned char byContntOffset) { unsigned short wDelay, wNoACK; @@ -81,18 +77,18 @@ unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, unsigned char byOrg; byData = 0xFF; - VNSvInPortB(dwIoBase + MAC_REG_I2MCFG, &byOrg); + VNSvInPortB(iobase + MAC_REG_I2MCFG, &byOrg); /* turn off hardware retry for getting NACK */ - VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, (byOrg & (~I2MCFG_NORETRY))); + VNSvOutPortB(iobase + MAC_REG_I2MCFG, (byOrg & (~I2MCFG_NORETRY))); for (wNoACK = 0; wNoACK < W_MAX_I2CRETRY; wNoACK++) { - VNSvOutPortB(dwIoBase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID); - VNSvOutPortB(dwIoBase + MAC_REG_I2MTGAD, byContntOffset); + VNSvOutPortB(iobase + MAC_REG_I2MTGID, EEP_I2C_DEV_ID); + VNSvOutPortB(iobase + MAC_REG_I2MTGAD, byContntOffset); /* issue read command */ - VNSvOutPortB(dwIoBase + MAC_REG_I2MCSR, I2MCSR_EEMR); + VNSvOutPortB(iobase + MAC_REG_I2MCSR, I2MCSR_EEMR); /* wait DONE be set */ for (wDelay = 0; wDelay < W_MAX_TIMEOUT; wDelay++) { - VNSvInPortB(dwIoBase + MAC_REG_I2MCSR, &byWait); + VNSvInPortB(iobase + MAC_REG_I2MCSR, &byWait); if (byWait & (I2MCSR_DONE | I2MCSR_NACK)) break; PCAvDelayByIO(CB_DELAY_LOOP_WAIT); @@ -102,8 +98,8 @@ unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, break; } } - VNSvInPortB(dwIoBase + MAC_REG_I2MDIPT, &byData); - VNSvOutPortB(dwIoBase + MAC_REG_I2MCFG, byOrg); + VNSvInPortB(iobase + MAC_REG_I2MDIPT, &byData); + VNSvOutPortB(iobase + MAC_REG_I2MCFG, byOrg); return byData; } @@ -112,20 +108,20 @@ unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * Out: * pbyEepromRegs - EEPROM content Buffer * * Return Value: none * */ -void SROMvReadAllContents(void __iomem *dwIoBase, unsigned char *pbyEepromRegs) +void SROMvReadAllContents(void __iomem *iobase, unsigned char *pbyEepromRegs) { int ii; /* ii = Rom Address */ for (ii = 0; ii < EEP_MAX_CONTEXT_SIZE; ii++) { - *pbyEepromRegs = SROMbyReadEmbedded(dwIoBase, + *pbyEepromRegs = SROMbyReadEmbedded(iobase, (unsigned char)ii); pbyEepromRegs++; } @@ -136,21 +132,21 @@ void SROMvReadAllContents(void __iomem *dwIoBase, unsigned char *pbyEepromRegs) * * Parameters: * In: - * dwIoBase - I/O base address + * iobase - I/O base address * Out: * pbyEtherAddress - Ethernet Address buffer * * Return Value: none * */ -void SROMvReadEtherAddress(void __iomem *dwIoBase, +void SROMvReadEtherAddress(void __iomem *iobase, unsigned char *pbyEtherAddress) { unsigned char ii; /* ii = Rom Address */ for (ii = 0; ii < ETH_ALEN; ii++) { - *pbyEtherAddress = SROMbyReadEmbedded(dwIoBase, ii); + *pbyEtherAddress = SROMbyReadEmbedded(iobase, ii); pbyEtherAddress++; } } diff --git a/drivers/staging/vt6655/srom.h b/drivers/staging/vt6655/srom.h index 531bf0069373..6e03ab6dfa9d 100644 --- a/drivers/staging/vt6655/srom.h +++ b/drivers/staging/vt6655/srom.h @@ -12,11 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * * File: srom.h * * Purpose: Implement functions to access eeprom @@ -90,12 +85,12 @@ /*--------------------- Export Functions --------------------------*/ -unsigned char SROMbyReadEmbedded(void __iomem *dwIoBase, +unsigned char SROMbyReadEmbedded(void __iomem *iobase, unsigned char byContntOffset); -void SROMvReadAllContents(void __iomem *dwIoBase, unsigned char *pbyEepromRegs); +void SROMvReadAllContents(void __iomem *iobase, unsigned char *pbyEepromRegs); -void SROMvReadEtherAddress(void __iomem *dwIoBase, +void SROMvReadEtherAddress(void __iomem *iobase, unsigned char *pbyEtherAddress); #endif /* __EEPROM_H__*/ diff --git a/drivers/staging/vt6655/tmacro.h b/drivers/staging/vt6655/tmacro.h index 597efefc017f..d6a0563ad55c 100644 --- a/drivers/staging/vt6655/tmacro.h +++ b/drivers/staging/vt6655/tmacro.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: tmacro.h * * Purpose: define basic common types and macros diff --git a/drivers/staging/vt6655/upc.h b/drivers/staging/vt6655/upc.h index 85fe0464cfb3..9806b5989014 100644 --- a/drivers/staging/vt6655/upc.h +++ b/drivers/staging/vt6655/upc.h @@ -12,10 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * * File: upc.h * * Purpose: Macros to access device |