diff options
Diffstat (limited to 'drivers/staging')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 24 |
1 files changed, 1 insertions, 23 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 3b45c592d10f..4200c68eb65e 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -84,7 +84,6 @@ #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) #define RALINK_PCI_BASE 0xBE140000 -#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RT6855_PCIE0_OFFSET 0x2000 #define RT6855_PCIE1_OFFSET 0x3000 #define RT6855_PCIE2_OFFSET 0x4000 @@ -95,8 +94,6 @@ #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034) #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038) #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050) -#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060) -#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064) #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010) #define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018) @@ -104,8 +101,6 @@ #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034) #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038) #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050) -#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060) -#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064) #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010) #define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018) @@ -113,17 +108,10 @@ #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034) #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038) #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050) -#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060) -#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064) #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000) -#define MV_WRITE(ofs, data) \ - *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data) -#define MV_READ(ofs, data) \ - *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) - #define RALINK_PCI_MM_MAP_BASE 0x60000000 #define RALINK_PCI_IO_MAP_BASE 0x1e160000 @@ -141,28 +129,18 @@ else \ rt_sysc_m32(0, val, RALINK_RSTCTRL); \ } while (0) + #define RALINK_CLKCFG1 0x30 #define RALINK_RSTCTRL 0x34 #define RALINK_GPIOMODE 0x60 #define RALINK_PCIE_CLK_GEN 0x7c #define RALINK_PCIE_CLK_GEN1 0x80 -#define PPLL_CFG1 0x9c -#define PPLL_DRV 0xa0 -/* SYSC_REG_SYSTEM_CONFIG1 bits */ -#define RALINK_PCI_HOST_MODE_EN (1<<7) -#define RALINK_PCIE_RC_MODE_EN (1<<8) //RALINK_RSTCTRL bit #define RALINK_PCIE_RST (1<<23) #define RALINK_PCI_RST (1<<24) //RALINK_CLKCFG1 bit #define RALINK_PCI_CLK_EN (1<<19) #define RALINK_PCIE_CLK_EN (1<<21) -//RALINK_GPIOMODE bit -#define PCI_SLOTx2 (1<<11) -#define PCI_SLOTx1 (2<<11) -//MTK PCIE PLL bit -#define PDRV_SW_SET (1<<31) -#define LC_CKDRVPD_ (1<<19) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; |