diff options
Diffstat (limited to 'drivers/ufs/host/ufs-renesas.c')
| -rw-r--r-- | drivers/ufs/host/ufs-renesas.c | 723 |
1 files changed, 433 insertions, 290 deletions
diff --git a/drivers/ufs/host/ufs-renesas.c b/drivers/ufs/host/ufs-renesas.c index 03cd82db751b..5bf7d0e77ad8 100644 --- a/drivers/ufs/host/ufs-renesas.c +++ b/drivers/ufs/host/ufs-renesas.c @@ -9,324 +9,408 @@ #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/err.h> +#include <linux/firmware.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/nvmem-consumer.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/sys_soc.h> #include <ufs/ufshcd.h> #include "ufshcd-pltfrm.h" +#define EFUSE_CALIB_SIZE 8 + struct ufs_renesas_priv { + const struct firmware *fw; + void (*pre_init)(struct ufs_hba *hba); bool initialized; /* The hardware needs initialization once */ + u8 calib[EFUSE_CALIB_SIZE]; }; -enum { - SET_PHY_INDEX_LO = 0, - SET_PHY_INDEX_HI, - TIMER_INDEX, - MAX_INDEX -}; +#define UFS_RENESAS_FIRMWARE_NAME "r8a779f0_ufs.bin" +MODULE_FIRMWARE(UFS_RENESAS_FIRMWARE_NAME); -enum ufs_renesas_init_param_mode { - MODE_RESTORE, - MODE_SET, - MODE_SAVE, - MODE_POLL, - MODE_WAIT, - MODE_WRITE, -}; +static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba) +{ + ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + "); +} -#define PARAM_RESTORE(_reg, _index) \ - { .mode = MODE_RESTORE, .reg = _reg, .index = _index } -#define PARAM_SET(_index, _set) \ - { .mode = MODE_SET, .index = _index, .u.set = _set } -#define PARAM_SAVE(_reg, _mask, _index) \ - { .mode = MODE_SAVE, .reg = _reg, .mask = (u32)(_mask), \ - .index = _index } -#define PARAM_POLL(_reg, _expected, _mask) \ - { .mode = MODE_POLL, .reg = _reg, .u.expected = _expected, \ - .mask = (u32)(_mask) } -#define PARAM_WAIT(_delay_us) \ - { .mode = MODE_WAIT, .u.delay_us = _delay_us } - -#define PARAM_WRITE(_reg, _val) \ - { .mode = MODE_WRITE, .reg = _reg, .u.val = _val } - -#define PARAM_WRITE_D0_D4(_d0, _d4) \ - PARAM_WRITE(0xd0, _d0), PARAM_WRITE(0xd4, _d4) - -#define PARAM_WRITE_800_80C_POLL(_addr, _data_800) \ - PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \ - PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \ - PARAM_WRITE(0xd0, 0x0000080c), \ - PARAM_POLL(0xd4, BIT(8), BIT(8)) - -#define PARAM_RESTORE_800_80C_POLL(_index) \ - PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \ - PARAM_WRITE(0xd0, 0x00000800), \ - PARAM_RESTORE(0xd4, _index), \ - PARAM_WRITE(0xd0, 0x0000080c), \ - PARAM_POLL(0xd4, BIT(8), BIT(8)) - -#define PARAM_WRITE_804_80C_POLL(_addr, _data_804) \ - PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \ - PARAM_WRITE_D0_D4(0x00000804, ((_data_804) << 16) | BIT(8) | (_addr)), \ - PARAM_WRITE(0xd0, 0x0000080c), \ - PARAM_POLL(0xd4, BIT(8), BIT(8)) - -#define PARAM_WRITE_828_82C_POLL(_data_828) \ - PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000), \ - PARAM_WRITE_D0_D4(0x00000828, _data_828), \ - PARAM_WRITE(0xd0, 0x0000082c), \ - PARAM_POLL(0xd4, _data_828, _data_828) - -#define PARAM_WRITE_PHY(_addr16, _data16) \ - PARAM_WRITE(0xf0, 1), \ - PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x18, (_data16) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x19, ((_data16) >> 8) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE(0xf0, 0) - -#define PARAM_SET_PHY(_addr16, _data16) \ - PARAM_WRITE(0xf0, 1), \ - PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE_804_80C_POLL(0x1a, 0), \ - PARAM_WRITE(0xd0, 0x00000808), \ - PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_LO), \ - PARAM_WRITE_804_80C_POLL(0x1b, 0), \ - PARAM_WRITE(0xd0, 0x00000808), \ - PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_HI), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE(0xf0, 0), \ - PARAM_WRITE(0xf0, 1), \ - PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \ - PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \ - PARAM_SET(SET_PHY_INDEX_LO, ((_data16 & 0xff) << 16) | BIT(8) | 0x18), \ - PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_LO), \ - PARAM_SET(SET_PHY_INDEX_HI, (((_data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19), \ - PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_HI), \ - PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE(0xf0, 0) - -#define PARAM_INDIRECT_WRITE(_gpio, _addr, _data_800) \ - PARAM_WRITE(0xf0, _gpio), \ - PARAM_WRITE_800_80C_POLL(_addr, _data_800), \ - PARAM_WRITE_828_82C_POLL(0x0f000000), \ - PARAM_WRITE(0xf0, 0) - -#define PARAM_INDIRECT_POLL(_gpio, _addr, _expected, _mask) \ - PARAM_WRITE(0xf0, _gpio), \ - PARAM_WRITE_800_80C_POLL(_addr, 0), \ - PARAM_WRITE(0xd0, 0x00000808), \ - PARAM_POLL(0xd4, _expected, _mask), \ - PARAM_WRITE(0xf0, 0) - -struct ufs_renesas_init_param { - enum ufs_renesas_init_param_mode mode; - u32 reg; - union { - u32 expected; - u32 delay_us; - u32 set; - u32 val; - } u; - u32 mask; - u32 index; -}; +static void ufs_renesas_poll(struct ufs_hba *hba, u32 reg, u32 expected, u32 mask) +{ + int ret; + u32 val; -/* This setting is for SERIES B */ -static const struct ufs_renesas_init_param ufs_param[] = { - PARAM_WRITE(0xc0, 0x49425308), - PARAM_WRITE_D0_D4(0x00000104, 0x00000002), - PARAM_WAIT(1), - PARAM_WRITE_D0_D4(0x00000828, 0x00000200), - PARAM_WAIT(1), - PARAM_WRITE_D0_D4(0x00000828, 0x00000000), - PARAM_WRITE_D0_D4(0x00000104, 0x00000001), - PARAM_WRITE_D0_D4(0x00000940, 0x00000001), - PARAM_WAIT(1), - PARAM_WRITE_D0_D4(0x00000940, 0x00000000), - - PARAM_WRITE(0xc0, 0x49425308), - PARAM_WRITE(0xc0, 0x41584901), - - PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), - PARAM_WRITE_D0_D4(0x00000804, 0x00000000), - PARAM_WRITE(0xd0, 0x0000080c), - PARAM_POLL(0xd4, BIT(8), BIT(8)), - - PARAM_WRITE(REG_CONTROLLER_ENABLE, 0x00000001), - - PARAM_WRITE(0xd0, 0x00000804), - PARAM_POLL(0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)), - - PARAM_WRITE(0xd0, 0x00000d00), - PARAM_SAVE(0xd4, 0x0000ffff, TIMER_INDEX), - PARAM_WRITE(0xd4, 0x00000000), - PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000), - PARAM_WRITE_D0_D4(0x00000828, 0x08000000), - PARAM_WRITE(0xd0, 0x0000082c), - PARAM_POLL(0xd4, BIT(27), BIT(27)), - PARAM_WRITE(0xd0, 0x00000d2c), - PARAM_POLL(0xd4, BIT(0), BIT(0)), + ret = readl_poll_timeout_atomic(hba->mmio_base + reg, + val, (val & mask) == expected, + 10, 1000); + if (ret) + dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n", + __func__, ret, val, mask, expected); +} - /* phy setup */ - PARAM_INDIRECT_WRITE(1, 0x01, 0x001f), - PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x5e, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x0d, 0x0003), - PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007), - PARAM_INDIRECT_WRITE(7, 0x5f, 0x0003), - PARAM_INDIRECT_WRITE(7, 0x60, 0x0003), - PARAM_INDIRECT_WRITE(7, 0x5b, 0x00a6), - PARAM_INDIRECT_WRITE(7, 0x5c, 0x0003), - - PARAM_INDIRECT_POLL(7, 0x3c, 0, BIT(7)), - PARAM_INDIRECT_POLL(7, 0x4c, 0, BIT(4)), - - PARAM_INDIRECT_WRITE(1, 0x32, 0x0080), - PARAM_INDIRECT_WRITE(1, 0x1f, 0x0001), - PARAM_INDIRECT_WRITE(0, 0x2c, 0x0001), - PARAM_INDIRECT_WRITE(0, 0x32, 0x0087), - - PARAM_INDIRECT_WRITE(1, 0x4d, 0x0061), - PARAM_INDIRECT_WRITE(4, 0x9b, 0x0009), - PARAM_INDIRECT_WRITE(4, 0xa6, 0x0005), - PARAM_INDIRECT_WRITE(4, 0xa5, 0x0058), - PARAM_INDIRECT_WRITE(1, 0x39, 0x0027), - PARAM_INDIRECT_WRITE(1, 0x47, 0x004c), - - PARAM_INDIRECT_WRITE(7, 0x0d, 0x0002), - PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007), - - PARAM_WRITE_PHY(0x0028, 0x0061), - PARAM_WRITE_PHY(0x4014, 0x0061), - PARAM_SET_PHY(0x401c, BIT(2)), - PARAM_WRITE_PHY(0x4000, 0x0000), - PARAM_WRITE_PHY(0x4001, 0x0000), - - PARAM_WRITE_PHY(0x10ae, 0x0001), - PARAM_WRITE_PHY(0x10ad, 0x0000), - PARAM_WRITE_PHY(0x10af, 0x0001), - PARAM_WRITE_PHY(0x10b6, 0x0001), - PARAM_WRITE_PHY(0x10ae, 0x0000), - - PARAM_WRITE_PHY(0x10ae, 0x0001), - PARAM_WRITE_PHY(0x10ad, 0x0000), - PARAM_WRITE_PHY(0x10af, 0x0002), - PARAM_WRITE_PHY(0x10b6, 0x0001), - PARAM_WRITE_PHY(0x10ae, 0x0000), - - PARAM_WRITE_PHY(0x10ae, 0x0001), - PARAM_WRITE_PHY(0x10ad, 0x0080), - PARAM_WRITE_PHY(0x10af, 0x0000), - PARAM_WRITE_PHY(0x10b6, 0x0001), - PARAM_WRITE_PHY(0x10ae, 0x0000), - - PARAM_WRITE_PHY(0x10ae, 0x0001), - PARAM_WRITE_PHY(0x10ad, 0x0080), - PARAM_WRITE_PHY(0x10af, 0x001a), - PARAM_WRITE_PHY(0x10b6, 0x0001), - PARAM_WRITE_PHY(0x10ae, 0x0000), - - PARAM_INDIRECT_WRITE(7, 0x70, 0x0016), - PARAM_INDIRECT_WRITE(7, 0x71, 0x0016), - PARAM_INDIRECT_WRITE(7, 0x72, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x73, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x74, 0x0000), - PARAM_INDIRECT_WRITE(7, 0x75, 0x0000), - PARAM_INDIRECT_WRITE(7, 0x76, 0x0010), - PARAM_INDIRECT_WRITE(7, 0x77, 0x0010), - PARAM_INDIRECT_WRITE(7, 0x78, 0x00ff), - PARAM_INDIRECT_WRITE(7, 0x79, 0x0000), - - PARAM_INDIRECT_WRITE(7, 0x19, 0x0007), - - PARAM_INDIRECT_WRITE(7, 0x1a, 0x0007), - - PARAM_INDIRECT_WRITE(7, 0x24, 0x000c), - - PARAM_INDIRECT_WRITE(7, 0x25, 0x000c), - - PARAM_INDIRECT_WRITE(7, 0x62, 0x0000), - PARAM_INDIRECT_WRITE(7, 0x63, 0x0000), - PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014), - PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017), - PARAM_INDIRECT_WRITE(7, 0x5d, 0x0004), - PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017), - PARAM_INDIRECT_POLL(7, 0x55, 0, BIT(6)), - PARAM_INDIRECT_POLL(7, 0x41, 0, BIT(7)), - /* end of phy setup */ +static u32 ufs_renesas_read(struct ufs_hba *hba, u32 reg) +{ + return ufshcd_readl(hba, reg); +} - PARAM_WRITE(0xf0, 0), - PARAM_WRITE(0xd0, 0x00000d00), - PARAM_RESTORE(0xd4, TIMER_INDEX), -}; +static void ufs_renesas_write(struct ufs_hba *hba, u32 reg, u32 value) +{ + ufshcd_writel(hba, value, reg); +} -static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba) +static void ufs_renesas_write_d0_d4(struct ufs_hba *hba, u32 data_d0, u32 data_d4) { - ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + "); + ufs_renesas_write(hba, 0xd0, data_d0); + ufs_renesas_write(hba, 0xd4, data_d4); } -static void ufs_renesas_reg_control(struct ufs_hba *hba, - const struct ufs_renesas_init_param *p) +static void ufs_renesas_write_800_80c_poll(struct ufs_hba *hba, u32 addr, + u32 data_800) { - static u32 save[MAX_INDEX]; - int ret; - u32 val; + ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); + ufs_renesas_write_d0_d4(hba, 0x00000800, (data_800 << 16) | BIT(8) | addr); + ufs_renesas_write(hba, 0xd0, 0x0000080c); + ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); +} + +static void ufs_renesas_write_804_80c_poll(struct ufs_hba *hba, u32 addr, u32 data_804) +{ + ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); + ufs_renesas_write_d0_d4(hba, 0x00000804, (data_804 << 16) | BIT(8) | addr); + ufs_renesas_write(hba, 0xd0, 0x0000080c); + ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); +} + +static void ufs_renesas_write_828_82c_poll(struct ufs_hba *hba, u32 data_828) +{ + ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000); + ufs_renesas_write_d0_d4(hba, 0x00000828, data_828); + ufs_renesas_write(hba, 0xd0, 0x0000082c); + ufs_renesas_poll(hba, 0xd4, data_828, data_828); +} + +static void ufs_renesas_write_phy(struct ufs_hba *hba, u32 addr16, u32 data16) +{ + ufs_renesas_write(hba, 0xf0, 1); + ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x18, data16 & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x19, (data16 >> 8) & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01); + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write(hba, 0xf0, 0); +} + +static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16) +{ + u32 low, high; + + ufs_renesas_write(hba, 0xf0, 1); + ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff); + ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01); + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write_804_80c_poll(hba, 0x1a, 0); + ufs_renesas_write(hba, 0xd0, 0x00000808); + low = ufs_renesas_read(hba, 0xd4) & 0xff; + ufs_renesas_write_804_80c_poll(hba, 0x1b, 0); + ufs_renesas_write(hba, 0xd0, 0x00000808); + high = ufs_renesas_read(hba, 0xd4) & 0xff; + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write(hba, 0xf0, 0); + + data16 |= (high << 8) | low; + ufs_renesas_write_phy(hba, addr16, data16); +} + +static void ufs_renesas_reset_indirect_write(struct ufs_hba *hba, int gpio, + u32 addr, u32 data) +{ + ufs_renesas_write(hba, 0xf0, gpio); + ufs_renesas_write_800_80c_poll(hba, addr, data); +} + +static void ufs_renesas_reset_indirect_update(struct ufs_hba *hba) +{ + ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000); + ufs_renesas_write_d0_d4(hba, 0x00000828, 0x0f000000); + ufs_renesas_write(hba, 0xd0, 0x0000082c); + ufs_renesas_poll(hba, 0xd4, BIT(27) | BIT(26) | BIT(24), BIT(27) | BIT(26) | BIT(24)); + ufs_renesas_write(hba, 0xf0, 0); +} + +static void ufs_renesas_indirect_write(struct ufs_hba *hba, u32 gpio, u32 addr, + u32 data_800) +{ + ufs_renesas_write(hba, 0xf0, gpio); + ufs_renesas_write_800_80c_poll(hba, addr, data_800); + ufs_renesas_write_828_82c_poll(hba, 0x0f000000); + ufs_renesas_write(hba, 0xf0, 0); +} + +static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr, + u32 expected, u32 mask) +{ + ufs_renesas_write(hba, 0xf0, gpio); + ufs_renesas_write_800_80c_poll(hba, addr, 0); + ufs_renesas_write(hba, 0xd0, 0x00000808); + ufs_renesas_poll(hba, 0xd4, expected, mask); + ufs_renesas_write(hba, 0xf0, 0); +} + +static void ufs_renesas_init_step1_to_3(struct ufs_hba *hba, bool init108) +{ + ufs_renesas_write(hba, 0xc0, 0x49425308); + ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002); + if (init108) + ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000002); + udelay(1); + ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000200); + udelay(1); + ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000000); + ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000001); + if (init108) + ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000001); + ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000001); + udelay(1); + ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000000); + + ufs_renesas_write(hba, 0xc0, 0x49425308); + ufs_renesas_write(hba, 0xc0, 0x41584901); +} + +static void ufs_renesas_init_step4_to_6(struct ufs_hba *hba) +{ + ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); + ufs_renesas_write_d0_d4(hba, 0x00000804, 0x00000000); + ufs_renesas_write(hba, 0xd0, 0x0000080c); + ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); - WARN_ON(p->index >= MAX_INDEX); - - switch (p->mode) { - case MODE_RESTORE: - ufshcd_writel(hba, save[p->index], p->reg); - break; - case MODE_SET: - save[p->index] |= p->u.set; - break; - case MODE_SAVE: - save[p->index] = ufshcd_readl(hba, p->reg) & p->mask; - break; - case MODE_POLL: - ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg, - val, - (val & p->mask) == p->u.expected, - 10, 1000); - if (ret) - dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n", - __func__, ret, val, p->mask, p->u.expected); - break; - case MODE_WAIT: - if (p->u.delay_us > 1000) - mdelay(DIV_ROUND_UP(p->u.delay_us, 1000)); - else - udelay(p->u.delay_us); - break; - case MODE_WRITE: - ufshcd_writel(hba, p->u.val, p->reg); - break; - default: - break; + ufs_renesas_write(hba, REG_CONTROLLER_ENABLE, 0x00000001); + + ufs_renesas_write(hba, 0xd0, 0x00000804); + ufs_renesas_poll(hba, 0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)); +} + +static u32 ufs_renesas_init_disable_timer(struct ufs_hba *hba) +{ + u32 timer_val; + + ufs_renesas_write(hba, 0xd0, 0x00000d00); + timer_val = ufs_renesas_read(hba, 0xd4) & 0x0000ffff; + ufs_renesas_write(hba, 0xd4, 0x00000000); + ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000); + ufs_renesas_write_d0_d4(hba, 0x00000828, 0x08000000); + ufs_renesas_write(hba, 0xd0, 0x0000082c); + ufs_renesas_poll(hba, 0xd4, BIT(27), BIT(27)); + ufs_renesas_write(hba, 0xd0, 0x00000d2c); + ufs_renesas_poll(hba, 0xd4, BIT(0), BIT(0)); + + return timer_val; +} + +static void ufs_renesas_init_enable_timer(struct ufs_hba *hba, u32 timer_val) +{ + ufs_renesas_write(hba, 0xf0, 0); + ufs_renesas_write(hba, 0xd0, 0x00000d00); + ufs_renesas_write(hba, 0xd4, timer_val); +} + +static void ufs_renesas_write_phy_10ad_10af(struct ufs_hba *hba, + u32 data_10ad, u32 data_10af) +{ + ufs_renesas_write_phy(hba, 0x10ae, 0x0001); + ufs_renesas_write_phy(hba, 0x10ad, data_10ad); + ufs_renesas_write_phy(hba, 0x10af, data_10af); + ufs_renesas_write_phy(hba, 0x10b6, 0x0001); + ufs_renesas_write_phy(hba, 0x10ae, 0x0000); +} + +static void ufs_renesas_init_compensation_and_slicers(struct ufs_hba *hba) +{ + ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0001); + ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0002); + ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x0000); + ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x001a); +} + +static void ufs_renesas_r8a779f0_es10_pre_init(struct ufs_hba *hba) +{ + u32 timer_val; + + /* This setting is for SERIES B */ + ufs_renesas_init_step1_to_3(hba, false); + + ufs_renesas_init_step4_to_6(hba); + + timer_val = ufs_renesas_init_disable_timer(hba); + + /* phy setup */ + ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0003); + ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007); + ufs_renesas_indirect_write(hba, 7, 0x5f, 0x0003); + ufs_renesas_indirect_write(hba, 7, 0x60, 0x0003); + ufs_renesas_indirect_write(hba, 7, 0x5b, 0x00a6); + ufs_renesas_indirect_write(hba, 7, 0x5c, 0x0003); + + ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7)); + ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4)); + + ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080); + ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001); + ufs_renesas_indirect_write(hba, 0, 0x2c, 0x0001); + ufs_renesas_indirect_write(hba, 0, 0x32, 0x0087); + + ufs_renesas_indirect_write(hba, 1, 0x4d, 0x0061); + ufs_renesas_indirect_write(hba, 4, 0x9b, 0x0009); + ufs_renesas_indirect_write(hba, 4, 0xa6, 0x0005); + ufs_renesas_indirect_write(hba, 4, 0xa5, 0x0058); + ufs_renesas_indirect_write(hba, 1, 0x39, 0x0027); + ufs_renesas_indirect_write(hba, 1, 0x47, 0x004c); + + ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002); + ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007); + + ufs_renesas_write_phy(hba, 0x0028, 0x0061); + ufs_renesas_write_phy(hba, 0x4014, 0x0061); + ufs_renesas_set_phy(hba, 0x401c, BIT(2)); + ufs_renesas_write_phy(hba, 0x4000, 0x0000); + ufs_renesas_write_phy(hba, 0x4001, 0x0000); + + ufs_renesas_init_compensation_and_slicers(hba); + + ufs_renesas_indirect_write(hba, 7, 0x70, 0x0016); + ufs_renesas_indirect_write(hba, 7, 0x71, 0x0016); + ufs_renesas_indirect_write(hba, 7, 0x72, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x73, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x74, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x75, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x76, 0x0010); + ufs_renesas_indirect_write(hba, 7, 0x77, 0x0010); + ufs_renesas_indirect_write(hba, 7, 0x78, 0x00ff); + ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000); + + ufs_renesas_indirect_write(hba, 7, 0x19, 0x0007); + ufs_renesas_indirect_write(hba, 7, 0x1a, 0x0007); + ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c); + ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c); + ufs_renesas_indirect_write(hba, 7, 0x62, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x63, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017); + ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6)); + ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7)); + /* end of phy setup */ + + ufs_renesas_init_enable_timer(hba, timer_val); +} + +static void ufs_renesas_r8a779f0_init_step3_add(struct ufs_hba *hba, bool assert) +{ + u32 val_2x = 0, val_3x = 0, val_4x = 0; + + if (assert) { + val_2x = 0x0001; + val_3x = 0x0003; + val_4x = 0x0001; } + + ufs_renesas_reset_indirect_write(hba, 7, 0x20, val_2x); + ufs_renesas_reset_indirect_write(hba, 7, 0x4a, val_4x); + ufs_renesas_reset_indirect_write(hba, 7, 0x35, val_3x); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_reset_indirect_write(hba, 7, 0x21, val_2x); + ufs_renesas_reset_indirect_write(hba, 7, 0x4b, val_4x); + ufs_renesas_reset_indirect_write(hba, 7, 0x36, val_3x); + ufs_renesas_reset_indirect_update(hba); } -static void ufs_renesas_pre_init(struct ufs_hba *hba) +static void ufs_renesas_r8a779f0_pre_init(struct ufs_hba *hba) { - const struct ufs_renesas_init_param *p = ufs_param; - unsigned int i; + struct ufs_renesas_priv *priv = ufshcd_get_variant(hba); + u32 timer_val; + u32 data; + int i; + + /* This setting is for SERIES B */ + ufs_renesas_init_step1_to_3(hba, true); + + ufs_renesas_r8a779f0_init_step3_add(hba, true); + ufs_renesas_reset_indirect_write(hba, 7, 0x5f, 0x0063); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_reset_indirect_write(hba, 7, 0x60, 0x0003); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_reset_indirect_write(hba, 7, 0x5b, 0x00a6); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_reset_indirect_write(hba, 7, 0x5c, 0x0003); + ufs_renesas_reset_indirect_update(hba); + ufs_renesas_r8a779f0_init_step3_add(hba, false); + + ufs_renesas_init_step4_to_6(hba); + + timer_val = ufs_renesas_init_disable_timer(hba); + + ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0007); + ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007); + + ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7)); + ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4)); + + ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080); + ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001); + ufs_renesas_indirect_write(hba, 1, 0x2c, 0x0001); + ufs_renesas_indirect_write(hba, 1, 0x32, 0x0087); + + ufs_renesas_indirect_write(hba, 1, 0x4d, priv->calib[2]); + ufs_renesas_indirect_write(hba, 1, 0x4e, priv->calib[3]); + ufs_renesas_indirect_write(hba, 1, 0x0d, 0x0006); + ufs_renesas_indirect_write(hba, 1, 0x0e, 0x0007); + ufs_renesas_write_phy(hba, 0x0028, priv->calib[3]); + ufs_renesas_write_phy(hba, 0x4014, priv->calib[3]); + + ufs_renesas_set_phy(hba, 0x401c, BIT(2)); + + ufs_renesas_write_phy(hba, 0x4000, priv->calib[6]); + ufs_renesas_write_phy(hba, 0x4001, priv->calib[7]); + + ufs_renesas_indirect_write(hba, 1, 0x14, 0x0001); + + ufs_renesas_init_compensation_and_slicers(hba); + + ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000); + ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c); + ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c); + ufs_renesas_indirect_write(hba, 7, 0x62, 0x00c0); + ufs_renesas_indirect_write(hba, 7, 0x63, 0x0001); + + for (i = 0; i < priv->fw->size / 2; i++) { + data = (priv->fw->data[i * 2 + 1] << 8) | priv->fw->data[i * 2]; + ufs_renesas_write_phy(hba, 0xc000 + i, data); + } - for (i = 0; i < ARRAY_SIZE(ufs_param); i++) - ufs_renesas_reg_control(hba, &p[i]); + ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002); + ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007); + + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017); + ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004); + ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017); + ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6)); + ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7)); + + ufs_renesas_init_enable_timer(hba, timer_val); } static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba, @@ -338,7 +422,7 @@ static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba, return 0; if (status == PRE_CHANGE) - ufs_renesas_pre_init(hba); + priv->pre_init(hba); priv->initialized = true; @@ -356,20 +440,78 @@ static int ufs_renesas_setup_clocks(struct ufs_hba *hba, bool on, return 0; } +static const struct soc_device_attribute ufs_fallback[] = { + { .soc_id = "r8a779f0", .revision = "ES1.[01]" }, + { /* Sentinel */ } +}; + static int ufs_renesas_init(struct ufs_hba *hba) { + const struct soc_device_attribute *attr; + struct nvmem_cell *cell = NULL; + struct device *dev = hba->dev; struct ufs_renesas_priv *priv; + u8 *data = NULL; + size_t len; + int ret; - priv = devm_kzalloc(hba->dev, sizeof(*priv), GFP_KERNEL); + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; ufshcd_set_variant(hba, priv); hba->quirks |= UFSHCD_QUIRK_HIBERN_FASTAUTO; + attr = soc_device_match(ufs_fallback); + if (attr) + goto fallback; + + ret = request_firmware(&priv->fw, UFS_RENESAS_FIRMWARE_NAME, dev); + if (ret) { + dev_warn(dev, "Failed to load firmware\n"); + goto fallback; + } + + cell = nvmem_cell_get(dev, "calibration"); + if (IS_ERR(cell)) { + dev_warn(dev, "No calibration data specified\n"); + goto fallback; + } + + data = nvmem_cell_read(cell, &len); + if (IS_ERR(data)) { + dev_warn(dev, "Failed to read calibration data: %pe\n", data); + goto fallback; + } + + if (len != EFUSE_CALIB_SIZE) { + dev_warn(dev, "Invalid calibration data size %zu\n", len); + goto fallback; + } + + memcpy(priv->calib, data, EFUSE_CALIB_SIZE); + priv->pre_init = ufs_renesas_r8a779f0_pre_init; + goto out; + +fallback: + dev_info(dev, "Using ES1.0 init code\n"); + priv->pre_init = ufs_renesas_r8a779f0_es10_pre_init; + +out: + kfree(data); + if (!IS_ERR_OR_NULL(cell)) + nvmem_cell_put(cell); + return 0; } +static void ufs_renesas_exit(struct ufs_hba *hba) +{ + struct ufs_renesas_priv *priv = ufshcd_get_variant(hba); + + release_firmware(priv->fw); +} + static int ufs_renesas_set_dma_mask(struct ufs_hba *hba) { return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); @@ -378,6 +520,7 @@ static int ufs_renesas_set_dma_mask(struct ufs_hba *hba) static const struct ufs_hba_variant_ops ufs_renesas_vops = { .name = "renesas", .init = ufs_renesas_init, + .exit = ufs_renesas_exit, .set_dma_mask = ufs_renesas_set_dma_mask, .setup_clocks = ufs_renesas_setup_clocks, .hce_enable_notify = ufs_renesas_hce_enable_notify, |