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path: root/arch/arc/mm/tlb.c
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* ARC: mm: support 3 levels of page tablesVineet Gupta2021-08-261-2/+2
* ARC: mm: switch pgtable_t back to struct page *Vineet Gupta2021-08-261-37/+0
* ARC: mm: move MMU specific bits out of ASID allocatorVineet Gupta2021-08-241-7/+4
* ARC: mm: Fixes to allow STRICT_MM_TYPECHECKSVineet Gupta2021-08-241-5/+8
* ARC: mm: remove tlb paranoid codeVineet Gupta2021-08-241-40/+0
* ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 onlyVineet Gupta2021-08-241-2/+2
* ARC: retire MMUv1 and MMUv2 supportVineet Gupta2021-08-241-145/+18
* ARC: mm: PAE: use 40-bit physical page maskVladimir Isaev2021-05-101-1/+1
* ARC: mm: fix spelling mistakesFlavio Suligoi2020-11-171-12/+12
* ARC: mm: tlb flush optim: elide redundant uTLB invalidates for MMUv3Vineet Gupta2019-10-281-5/+0
* ARC: mm: tlb flush optim: elide repeated uTLB invalidate in loopVineet Gupta2019-10-281-45/+29
* ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch regVineet Gupta2019-10-281-1/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
* ARC: fix build warningsVineet Gupta2019-05-201-5/+8
* ARCv2: Accomodate HS48 MMUv5 by relaxing MMU ver checkingVineet Gupta2017-11-061-24/+33
* ARC: Re-enable MMU upon Machine Check exceptionJose Abreu2017-09-011-3/+0
* ARC: set boot print log level to PR_INFONoam Camus2017-08-281-1/+1
* ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoCVineet Gupta2017-08-041-1/+11
* sched/headers: Prepare to remove the <linux/mm_types.h> dependency from <linu...Ingo Molnar2017-03-021-0/+2
* ARC: boot log: remove awkward space comma from MMU lineVineet Gupta2016-10-281-3/+3
* ARC: [plat-eznps] Use dedicated user stack topNoam Camus2016-05-091-0/+6
* ARC: Make vmalloc size configurableNoam Camus2016-05-091-0/+5
* ARC: Fix misspellings in comments.Adam Buchbinder2016-03-111-4/+4
* ARC: comments updateVineet Gupta2015-11-161-2/+2
* ARC: mm: PAE40 supportVineet Gupta2015-10-291-5/+22
* ARC: mm: PAE40: switch to using phys_addr_t for physical addressesVineet Gupta2015-10-281-5/+5
* ARC: mm: Improve Duplicate PD Fault handlerVineet Gupta2015-10-281-24/+24
* ARC: boot log: decode more mmu config itemsVineet Gupta2015-10-171-6/+8
* ARC: boot log: move helper macros to header for reuseVineet Gupta2015-10-171-1/+1
* ARC: mm: compute TLB size as needed from ways * setsVineet Gupta2015-10-171-5/+4
* ARCv2: mm: THP: flush_pmd_tlb_range make SMP safeVineet Gupta2015-10-171-2/+25
* ARCv2: mm: THP: Implement flush_pmd_tlb_range() optimizationVineet Gupta2015-10-171-0/+20
* ARCv2: mm: THP: boot validation/reportingVineet Gupta2015-10-171-1/+7
* ARCv2: mm: THP supportVineet Gupta2015-10-171-0/+81
* ARCv2: MMUv4: TLB programming Model changesVineet Gupta2015-06-221-3/+51
* ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)Vineet Gupta2015-06-191-4/+4
* ARC: boot: cpu feature print enhancementsVineet Gupta2014-10-131-5/+3
* ARC: [SMP] TLB flushVineet Gupta2013-11-061-0/+73
* ARC: [SMP] ASID allocationVineet Gupta2013-11-061-6/+8
* ARC: Fix bogus gcc warning and micro-optimise TLB iteration loopVineet Gupta2013-11-061-2/+2
* ARC: [ASID] Track ASID allocation cycles/generationsVineet Gupta2013-08-301-15/+7
* ARC: [ASID] get_new_mmu_context() to conditionally allocate new ASIDVineet Gupta2013-08-301-6/+7
* ARC: [ASID] Refactor the TLB paranoid debug codeVineet Gupta2013-08-301-11/+13
* ARC: No need to flush the TLB in early bootVineet Gupta2013-08-301-7/+0
* ARC: MMUv4 preps/3 - Abstract out TLB Insert/DeleteVineet Gupta2013-08-301-40/+54
* ARC: MMUv4 preps/2 - Reshuffle PTE bitsVineet Gupta2013-08-301-8/+3
* ARC: MMUv4 preps/1 - Fold PTE K/U access flagsVineet Gupta2013-08-291-2/+17
* arc: delete __cpuinit usage from all arc filesPaul Gortmaker2013-06-271-2/+2
* ARC: [mm] Assume pagecache page dirty by defaultVineet Gupta2013-06-221-1/+1
* ARC: [mm] Zero page optimizationVineet Gupta2013-06-221-1/+5
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