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The PXA sub-architecture appears to have a custom <mach/gpio.h>
for no reason whatsoever. The file became completely empty
after Haojian removed the remaining content in
commit 157d2644cb0c1e71a18baaffca56d2b1d0ebf10f
"ARM: pxa: change gpio to platform device".
That commit added these two lines:
However it seems like deleting the file has no effect
whatsoever on the kernel compilation.
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Remove most gpio macros and change gpio driver to platform driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
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NR_BUILTIN_GPIO is both defined in arch-pxa and arch-mmp. Now replace it
with PXA_NR_BUILTIN_GPIO and MMP_NR_BUILTIN_GPIO.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
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Avoid to define gpio_to_irq() and irq_to_gpio() for potential name
confliction since multiple architecture will be built together.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
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GPIO0 and GPIO1 are linked to unique interrupt line in PXA series,
others are linked to another interrupt line. All GPIO are linked to one
interrupt line in MMP series.
Since gpio driver is shared between PXA series and MMP series, define
GPIO0 and GPIO1 as chained interrupt chip. So we can move out gpio code
from irq.c to gpio-pxa.c.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
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Avoid potential naming confliction since multiple architecture will be built
in a single kernel.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
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The <mach/gpio.h> file is included from upper directories
and deal with generic GPIO and gpiolib stuff. Break out the
platform and driver specific defines and functions into its own
header file.
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This fixes the failure to register the IRQ_RTCAlrm alarm as a wakeup
event. It is misinterpreted as a gpio irq not a PWER bitmask. Fixed
this by converting the incorrect IRQ_TO_IRQ() to a correct version of
irq_to_gpio().
Reported-by: Nick Bane <nickbane1@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Avoid to mismatch between NR_BUILTIN_GPIO and GPIO interrupt number
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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1. add common GPIO handling code into [arch/arm/plat-pxa]
2. common code in <mach/gpio.h> moved into <plat/gpio.h>, new processors
should implement its own <mach/gpio.h>, provide the following required
definitions and '#include <plat/gpio.h>' in the end:
- GPIO_REGS_VIRT for mapped virtual address of the GPIO registers'
physical I/O memory
- macros of GPLR(), GPSR(), GPDR() for constant optimization for
functions gpio_{set,get}_value() (so that bit-bang code can still
have tolerable performance)
- NR_BUILTIN_GPIO for the number of onchip GPIO
- definitions of __gpio_is_inverted() and __gpio_is_occupied(), they
can be either macros or inlined functions
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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The typo was originally fixed by Mike Rapoport and missed. And is
later reported by Matthias Meier.
Signed-off-by: Matthias Meier <matthias.j.meier@gmx.net>
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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Let's handle GPIOs by banks, each bank covers up to 32 GPIOs with one set
of registers, and each set of registers start from different offsets.
GPLR GPDR GPSR GPCR GRER GFER GEDR
BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
NOTE:
BANK 3 is only available on PXA27x and later processors.
BANK 4 and 5 are only available on PXA935
1. introduce GPIO_BANK(n) for the offset base of each bank
2. 'struct pxa_gpio_chip' is expanded to include IRQ edge and mask
setings, and saved register values as well, and is dynamically
allocated due to possible bank number ranging from 3 to 6
3. all accesses to GPIO registers are made through 'regbase' within
'pxa_gpio_chip', and register offset
4. introduce several inline functions to simplify the code a bit
5. change IRQ demux handler to base on gpio chips
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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Signed-off-by: Eric Miao <eric.miao@marvell.com>
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This makes gpio.c fully independent of pxa-regs.h (except for the
virtual address of the registers).
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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This is part of the work making gpio.c generic enough, the changes
include:
1. move IRQ handling of GPIO 0 and 1 outside (and back into irq.c)
2. pxa_init_gpio() accepts a range for muxed GPIO IRQs, and an IRQ
number for the muxed GPIOs
3. __gpio_is_occupied() and __gpio_is_inverted() are made inline,
and are moved into <mach/gpio.h> instead of generic gpio.c
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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