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* ARM: sti: Drop unused includesRob Herring2023-08-121-2/+0
| | | | | | | | | Several includes are not needed, so drop them. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20230803-dt-header-cleanups-for-soc-v2-2-d8de2cc88bff@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Revert "ARM: sti: Implement dummy L2 cache's write_sec"Patrice Chotard2020-06-281-9/+0
| | | | | | | | | | | | | | | | | | | This reverts commit 7b8e0188fa717cd9abc4fb52587445b421835c2a. Initially, STiH410-B2260 was supposed to be secured, that's why l2c_write_sec was stubbed to avoid secure register access from non secure world. But by default, STiH410-B2260 is running in non secure mode, so L2 cache register accesses are authorized, l2c_write_sec stub is not needed. With this patch, L2 cache is configured and performance are enhanced. Link: https://lore.kernel.org/r/20200618172456.29475-1-patrice.chotard@st.com Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Cc: Alain Volmat <alain.volmat@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: sti: Implement dummy L2 cache's write_secPatrice Chotard2016-07-111-0/+9
| | | | | | | | | This patch implements the write_sec callback that handle PL310 secure registers writes. This callback is just a stub for now, to avoid system crash. Later, it could handle SMC calls so that TZ handles the needed writes. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* ARM: STi: Update machine _namestr to be more generic.Peter Griffin2016-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This string is used by dump_stack and as we now support more SoC's than just STiH415/6 it is misleading to have the current string in the stack trace. This patch updates it to be more generic for the STi family of SoCs. So instead of looking like this [ 271.672555] Hardware name: STiH415/416 SoC with Flattened Device Tree [ 271.678998] [<c0310490>] (unwind_backtrace) from [<c030bb54>] (show_stack+0x10/0x14) [ 271.686746] [<c030bb54>] (show_stack) from [<c058bc4c>] (dump_stack+0x98/0xac) [snip] it now looks like this: [ 2.669879] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.6.0-rc3-00026-g38a1ce6-dirty #76 [ 2.677973] Hardware name: STi SoC with Flattened Device Tree [ 2.683723] [<c0310490>] (unwind_backtrace) from [<c030bb54>] (show_stack+0x10/0x14) [ 2.691472] [<c030bb54>] (show_stack) from [<c058bc0c>] (dump_stack+0x98/0xac) [snip] Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com>
* ARM: appropriate __init annotation for const dataNicolas Pitre2015-07-281-1/+1
| | | | | | | | | | Init data marked const should be annotated with __initconst for correctness and not __initdata. In some cases the array gathering references to that data has to be marked const as well. This fixes LTO builds that otherwise fail with section mismatch errors. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: STi: Add STiH410 SoC supportFabrice GASNIER2015-03-111-0/+1
| | | | | | | | | | | | | | | This patch adds support to STiH410 SoC. Please note "st,stih410" is already present in device tree. The problem is that it is missing the entry in the match table, and so the L2 cache and other cpus than 0 don't get initialized. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Tested-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: STi: Add STiH418 SoC supportMaxime COQUELIN2015-01-161-0/+1
| | | | | | This patch adds support to STiH418 SoC. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into nextLinus Torvalds2014-06-051-21/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: - Major clean-up of the L2 cache support code. The existing mess was becoming rather unmaintainable through all the additions that others have done over time. This turns it into a much nicer structure, and implements a few performance improvements as well. - Clean up some of the CP15 control register tweaks for alignment support, moving some code and data into alignment.c - DMA properties for ARM, from Santosh and reviewed by DT people. This adds DT properties to specify bus translations we can't discover automatically, and to indicate whether devices are coherent. - Hibernation support for ARM - Make ftrace work with read-only text in modules - add suspend support for PJ4B CPUs - rework interrupt masking for undefined instruction handling, which allows us to enable interrupts earlier in the handling of these exceptions. - support for big endian page tables - fix stacktrace support to exclude stacktrace functions from the trace, and add save_stack_trace_regs() implementation so that kprobes can record stack traces. - Add support for the Cortex-A17 CPU. - Remove last vestiges of ARM710 support. - Removal of ARM "meminfo" structure, finally converting us solely to memblock to handle the early memory initialisation. * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits) ARM: ensure C page table setup code follows assembly code (part II) ARM: ensure C page table setup code follows assembly code ARM: consolidate last remaining open-coded alignment trap enable ARM: remove global cr_no_alignment ARM: remove CPU_CP15 conditional from alignment.c ARM: remove unused adjust_cr() function ARM: move "noalign" command line option to alignment.c ARM: provide common method to clear bits in CPU control register ARM: 8025/1: Get rid of meminfo ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type ARM: 8066/1: correction for ARM patch 8031/2 ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation ARM: 8065/1: remove last use of CONFIG_CPU_ARM710 ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction ARM: 8047/1: rwsem: use asm-generic rwsem implementation ARM: l2c: trial at enabling some Cortex-A9 optimisations ARM: l2c: add warnings for stuff modifying aux_ctrl register values ARM: l2c: print a warning with L2C-310 caches if the cache size is modified ARM: l2c: remove old .set_debug method ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this ...
| * ARM: l2c: sti: convert to generic l2c OF initialisationRussell King2014-05-301-21/+6
| | | | | | | | | | | | | | | | Remove the explicit call to l2x0_of_init(), converting to the generic infrastructure instead. We can remove the .init_machine as it becomes the same as the generic version. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: l2c: fix register namingRussell King2014-05-301-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: STi: Add STiH407 SoC supportMaxime Coquelin2014-05-171-0/+1
|/ | | | | | | | This patch adds support to STiH407 SoC. Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: sti: remove custom .init_time hookSebastian Hesselbarth2013-09-291-6/+4
| | | | | | | | | With arch/arm calling of_clk_init(NULL) from time_init(), we can now remove custom .init_time hooks. To get rid of it, move l2cc init to .init_machine hook instead. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
* ARM: sti: Add STiH416 SOC supportSrinivas Kandagatla2013-06-251-1/+2
| | | | | | | | | | | | | | The STiH416 is advanced HD AVC processor with 3D graphics acceleration and 1.2-GHz ARM Cortex-A9 SMP CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: sti: Add STiH415 SOC supportSrinivas Kandagatla2013-06-251-0/+47
The STiH415 is the next generation of HD, AVC set-top box processors for satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9 1.0 GHz, dual-core CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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