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path: root/arch/mips/include/asm/r4kcache.h
Commit message (Expand)AuthorAgeFilesLines
* MIPS: Fix build error due to PTR used in more placesThomas Bogendoerfer2022-01-271-2/+2
* MIPS: Simplify EVA cache handlingThomas Bogendoerfer2021-02-131-56/+11
* MIPS: Loongson64: Rename CPU TYPESJiaxun Yang2019-10-311-2/+2
* MIPS: Provide unroll() macro, use it for cache opsPaul Burton2019-10-091-339/+19
* MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3Huacai Chen2018-11-201-0/+22
* MIPS: MT: Remove obsolete cache flush repeat codePaul Burton2018-09-261-73/+0
* new helper: uaccess_kernel()Al Viro2017-03-281-2/+2
* MIPS: Fix protected_cache(e)_op() for microMIPSPaul Burton2017-02-131-2/+4
* MIPS: Add return errors to protected cache opsJames Hogan2017-02-031-20/+35
* Replace <asm/uaccess.h> with <linux/uaccess.h> globallyLinus Torvalds2016-12-241-1/+1
* MIPS: c-r4k: Fix protected_writeback_scache_line for EVAJames Hogan2016-07-291-0/+4
* MIPS: r4kcache: Use correct base register for MIPS R6 cache flushesMarkos Chandras2015-04-101-44/+45
* MIPS: asm: r4kcache: Add MIPS R6 cache unroll functionsMarkos Chandras2015-02-171-2/+148
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-12-111-59/+0
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| * MIPS: Remove a temporary hack for debugging cache flushes in SMTC configurationRalf Baechle2014-11-241-59/+0
* | MIPS: r4kcache: Add EVA case for protected_writeback_dcache_lineMarkos Chandras2014-11-241-0/+4
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* MIPS: KVM: Reformat code and commentsDeng-Cheng Zhu2014-06-301-0/+3
* MIPS: Add minimal support for OCTEON3 to c-r4k.cDavid Daney2014-05-301-0/+2
* MIPS: MT: Remove SMTC supportRalf Baechle2014-05-241-3/+2
* MIPS: Fix gigaton of warning building with microMIPS.Ralf Baechle2014-03-311-2/+2
* MIPS: asm: r4kcache: Add EVA cache flushing functionsLeonid Yegoshin2014-03-261-1/+151
* MIPS: asm: r4kcache: Add protected cache operation for EVALeonid Yegoshin2014-03-261-0/+18
* MIPS: asm: r4kcache: Build flushing code for instruction cacheLeonid Yegoshin2014-03-261-0/+1
* MIPS: fix blast_icache32 on loongson2Aaro Koskinen2014-01-151-21/+22
* MIPS: fix case mismatch in local_r4k_flush_icache_range()Huacai Chen2014-01-151-4/+4
* MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.Ralf Baechle2013-10-291-11/+30
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-6/+6
* update David Miller's old email addressJustin P. Mattock2011-04-061-1/+1
* MIPS: Support 64-byte D-cache line sizeKevin Cernekee2009-06-171-0/+1
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-111-0/+443
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