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path: root/arch/mips/mm/c-r4k.c
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* MIPS: Add define for Config.VI (virtual icache) bitJames Hogan2016-06-151-1/+1
* MIPS: remove aliasing alignment if HW has antialising supportLeonid Yegoshin2016-05-131-1/+1
* MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENTHuacai Chen2016-05-131-0/+2
* MIPS: Loongson-3: Set cache flush handlers to cache_noopHuacai Chen2016-05-131-0/+14
* MIPS: Loongson: Add Loongson-3A R2 basic supportHuacai Chen2016-05-131-0/+27
* MIPS: BMIPS: local_r4k___flush_cache_all needs to blast S-cacheFlorian Fainelli2016-05-131-0/+5
* MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlierFlorian Fainelli2016-05-131-2/+2
* MIPS: BMIPS: BMIPS5000 has I cache filing from D cacheFlorian Fainelli2016-05-131-0/+4
* MIPS: Add M6250 cases to CPU switch statementsPaul Burton2016-05-131-0/+1
* MIPS: Add P6600 cases to CPU switch statementsPaul Burton2016-05-131-0/+1
* MIPS: I6400: Icache fills from dcacheJames Hogan2016-05-091-0/+1
* MIPS: c-r4k: Sync icache when it fills from dcacheJames Hogan2016-05-091-2/+9
* mm: differentiate page_mapped() from page_mapcount() for compound pagesKirill A. Shutemov2016-01-151-1/+2
* MIPS: Add cases for CPU_I6400Markos Chandras2015-08-261-0/+1
* MIPS: c-r4k: Extend way_string arrayPaul Burton2015-07-101-1/+3
* MIPS: c-r4k: Fix cache flushing for MT coresMarkos Chandras2015-07-101-3/+11
* MIPS: c-r4k: Remove legacy __cpuinit section that crept inPaul Gortmaker2015-06-211-1/+1
* MIPS: c-r4k: Fix typo in probe_scache()Joshua Kinard2015-06-061-1/+1
* MIPS: c-r4k.c: Fix the 74K D-cache alias erratum workaroundMaciej W. Rozycki2015-04-021-8/+15
* MIPS: Add R16000 detectionJoshua Kinard2015-04-011-3/+7
* MIPS: mm: scache: Add secondary cache support for MIPS R6 coresMarkos Chandras2015-02-171-1/+2
* MIPS: mm: c-r4k: Set the correct ISA levelMarkos Chandras2015-02-171-1/+1
* MIPS: Add cases for CPU_QEMU_GENERICLeonid Yegoshin2015-02-161-0/+1
* MIPS: BMIPS: Add special cache handling in c-r4k.cKevin Cernekee2014-11-241-0/+43
* MIPS: c-r4k: Avoid duplicate CPU_74K/CPU_1074K checksMaciej W. Rozycki2014-07-301-4/+4
* MIPS: Add minimal support for OCTEON3 to c-r4k.cDavid Daney2014-05-301-4/+44
* Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into mips-f...Ralf Baechle2014-05-291-0/+24
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| * MIPS: c-r4k: Add CPU PM callback for coherencyJames Hogan2014-05-021-0/+24
* | MIPS: MT: Remove SMTC supportRalf Baechle2014-05-241-2/+2
* | MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.Ralf Baechle2014-05-231-1/+0
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* MIPS: Loongson: Add basic Loongson-3 CPU supportHuacai Chen2014-03-311-0/+59
* MIPS: Add support for the M5150 processorLeonid Yegoshin2014-03-261-0/+1
* MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss2014-03-261-3/+3
* MIPS: mm: c-r4k: Flush scache to avoid cache aliasesLeonid Yegoshin2014-03-261-0/+11
* MIPS: mm: c-r4k: Add support for flushing user pages from cacheMarkos Chandras2014-03-261-2/+4
* MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functionsLeonid Yegoshin2014-03-261-0/+47
* MIPS: Add cases for CPU_P5600James Hogan2014-03-261-0/+1
* MIPS: Coherent Processing System SMP implementationPaul Burton2014-03-261-1/+1
* MIPS: Add 1074K CPU support explicitly.Steven J. Hill2014-03-061-1/+2
* MIPS: mm: c-r4k: Detect instruction cache aliasesMarkos Chandras2014-03-061-3/+8
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-01-301-8/+18
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| * MIPS: Add support for interAptiv coresLeonid Yegoshin2014-01-221-0/+1
| * MIPS: Add support for the proAptiv coresLeonid Yegoshin2014-01-221-0/+1
| * MIPS: mm: c-r4k: Panic if IL or DL fields have a reserved valueMarkos Chandras2014-01-221-8/+16
* | MIPS: fix blast_icache32 on loongson2Aaro Koskinen2014-01-151-0/+7
* | MIPS: fix case mismatch in local_r4k_flush_icache_range()Huacai Chen2014-01-151-2/+2
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* MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.Ralf Baechle2013-10-291-21/+31
* MIPS: Fix forgotten preempt_enable() when CPU has inclusive pcachesYoichi Yuasa2013-10-021-0/+2
* MIPS: 74K/1074K: Correct erratum workaround.Maciej W. Rozycki2013-09-181-8/+18
* MIPS: Cleanup CP0 PRId and CP1 FPIR register access masksMaciej W. Rozycki2013-09-181-5/+6
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