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path: root/arch/riscv/errata/sifive/errata.c
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* riscv: Extend cpufeature.c to detect vendor extensionsCharlie Jenkins2024-07-221-0/+3
* riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Samuel Holland2024-04-291-0/+5
* RISC-V: fix sifive and thead section mismatches in errataRandy Dunlap2023-04-291-5/+3
* Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-04-281-4/+4
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| * riscv: alternatives: Rename errata_id to patch_idAndrew Jones2023-03-141-3/+3
| * riscv: alternatives: Remove unnecessary define and unused structAndrew Jones2023-03-141-1/+1
* | RISC-V: fix taking the text_mutex twice during sifive errata patchingConor Dooley2023-03-071-1/+1
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* RISC-V: take text_mutex during alternative patchingConor Dooley2023-02-211-0/+3
* riscv: switch to relative alternative entriesJisheng Zhang2023-01-311-1/+2
* riscv: don't warn for sifive erratas in modulesHeiko Stuebner2022-07-071-1/+2
* riscv: add memory-type errata for T-HeadHeiko Stuebner2022-05-111-1/+6
* riscv: implement module alternativesHeiko Stuebner2022-05-111-5/+9
* riscv: allow different stages with alternativesHeiko Stuebner2022-05-111-1/+2
* riscv: sifive: Apply errata "cip-1200" patchVincent Chen2021-04-261-0/+18
* riscv: sifive: Apply errata "cip-453" patchVincent Chen2021-04-261-0/+20
* riscv: sifive: Add SiFive alternative portsVincent Chen2021-04-261-0/+68