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path: root/arch/riscv/include/asm/processor.h
Commit message (Expand)AuthorAgeFilesLines
* riscv: mm: Do not restrict mmap address based on hintCharlie Jenkins2024-08-291-24/+2
* riscv: hwprobe: export highest virtual userspace addressClément Léger2024-07-111-0/+6
* Merge patch series "riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX ...Palmer Dabbelt2024-04-301-0/+10
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| * riscv: Include riscv_set_icache_flush_ctx prctlCharlie Jenkins2024-04-181-0/+10
* | Merge patch series "riscv: Introduce compat-mode helpers & improve arch_get_m...Palmer Dabbelt2024-03-201-4/+8
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| * | riscv: add compile-time test into is_compat_task()Leonardo Bras2024-03-191-2/+2
| * | riscv: Improve arch_get_mmap_end() macroLeonardo Bras2024-03-191-3/+9
* | | Merge patch series "riscv: mm: Extend mappable memory up to hint address"Palmer Dabbelt2024-03-151-16/+11
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| * | riscv: mm: Use hint address in mmap if availableCharlie Jenkins2024-03-141-16/+11
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* | Merge patch series "riscv: support kernel-mode Vector"Palmer Dabbelt2024-01-161-1/+40
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| * | riscv: vector: allow kernel-mode Vector with preemptionAndy Chiu2024-01-161-1/+29
| * | riscv: vector: make Vector always available for softirq contextAndy Chiu2024-01-161-1/+2
| * | riscv: Add support for kernel mode vectorGreentime Hu2024-01-161-1/+11
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* / riscv: mm: Fixup compat arch_get_mmap_endGuo Ren2024-01-111-1/+1
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* Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-101-0/+9
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| * riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGNClément Léger2023-11-011-0/+9
* | riscv: kdump: use generic interface to simplify crashkernel reservationBaoquan He2023-10-041-0/+2
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* RISC-V: mm: Restrict address space for sv39,sv48,sv57Charlie Jenkins2023-08-231-6/+46
* Merge patch series "ISA string parser cleanups"Palmer Dabbelt2023-06-231-0/+1
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| * RISC-V: split early & late of_node to hartid mappingConor Dooley2023-06-211-0/+1
* | riscv: Add prctl controls for userspace vector managementAndy Chiu2023-06-081-0/+10
* | riscv: signal: Report signal frame size to userspace via auxvVincent Chen2023-06-081-0/+2
* | riscv: Add task switch support for vectorGreentime Hu2023-06-081-0/+1
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* kernel: exit: cleanup release_thread()Kefeng Wang2022-09-111-5/+0
* riscv: cpu: Add 64bit hartid support on RV64Sunil V L2022-07-191-2/+2
* riscv: compat: Support TASK_SIZE for compat modeGuo Ren2022-04-261-1/+5
* sched: Add wrapper for get_wchan() to keep task blockedKees Cook2021-10-151-1/+1
* riscv: Implement thread_struct whitelist for hardened usercopyTong Tiangen2021-08-031-0/+8
* riscv: process: Fix no prototype for arch_dup_task_structNanyong Sun2021-03-091-0/+1
* riscv: Add uprobes supportedGuo Ren2021-01-141-0/+1
* riscv: use vDSO common flow to reduce the latency of the time-related functionsVincent Chen2020-06-101-10/+2
* RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel2020-06-091-0/+1
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-1/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* riscv: Adjust mmap base address at a third of task sizeAlexandre Ghiti2019-01-251-1/+1
* treewide: remove current_text_addrNick Desaulniers2018-10-311-6/+0
* RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-221-1/+1
* RISC-V: Task implementationPalmer Dabbelt2017-09-261-0/+97
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