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* riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HWJisheng Zhang2024-01-092-0/+42
* Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-1016-120/+415
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| * riscv: Optimize bitops with Zbb extensionXiao Wang2023-11-091-3/+251
| * riscv: Rearrange hwcap.h and cpufeature.hXiao Wang2023-11-096-94/+87
| * Merge patch "drivers: perf: Do not broadcast to other cpus when starting a co...Palmer Dabbelt2023-11-093-2/+43
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| * | RISC-V: Probe misaligned access speed in parallelEvan Green2023-11-071-1/+0
| * | Merge patch series "riscv: tlb flush improvements"Palmer Dabbelt2023-11-063-8/+18
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| | * | riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti2023-11-061-5/+6
| | * | riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti2023-11-062-3/+3
| | * | riscv: Improve tlb_flush()Alexandre Ghiti2023-11-062-1/+10
| * | | riscv: mm: update T-Head memory type definitionsJisheng Zhang2023-11-051-5/+9
| * | | Merge patch series "Improve PTDUMP and introduce new fields"Palmer Dabbelt2023-11-051-2/+2
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| | * | | riscv: Improve PTDUMP to show RSW with non-zero valueYu Chien Peter Lin2023-11-051-2/+2
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| * | | RISC-V: capitalise CMO op macrosConor Dooley2023-11-052-7/+7
| * | | Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-053-0/+41
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| | * | | riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGNClément Léger2023-11-011-0/+9
| | * | | riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-011-0/+18
| | * | | riscv: add support for misaligned trap handling in S-modeClément Léger2023-11-011-0/+14
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* | | | Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-0814-17/+154
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| * | | RISC-V: hwprobe: Fix vDSO SIGSEGVAndrew Jones2023-11-021-0/+5
| * | | Merge patch series "riscv: SCS support"Palmer Dabbelt2023-11-025-4/+111
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| | * | | riscv: Use separate IRQ shadow call stacksSami Tolvanen2023-10-271-0/+7
| | * | | riscv: Implement Shadow Call StackSami Tolvanen2023-10-273-0/+66
| | * | | riscv: Move global pointer loading to a macroSami Tolvanen2023-10-271-0/+8
| | * | | riscv: Deduplicate IRQ stack switchingSami Tolvanen2023-10-272-0/+8
| | * | | riscv: VMAP_STACK overflow detection thread-safeDeepak Gupta2023-10-273-4/+22
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| * | | Merge patch "riscv: errata: improve T-Head CMO"Palmer Dabbelt2023-11-021-9/+9
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| | * | | riscv: errata: prefix T-Head mnemonics with th.Icenowy Zheng2023-11-021-7/+7
| * | | | Merge patch series "RISC-V: ACPI improvements"Palmer Dabbelt2023-10-311-0/+6
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| | * | | | RISC-V: ACPI: RHCT: Add function to get CBO block sizesSunil V L2023-10-261-0/+6
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| * | | | riscv: mm: Update the comment of CONFIG_PAGE_OFFSETSong Shuai2023-10-311-2/+2
| * | | | riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpauseMinda Chen2023-10-311-1/+1
| * | | | riscv/mm: Fix the comment for swap pte formatXiao Wang2023-10-311-1/+1
| * | | | RISC-V: Provide pgtable_l5_enabled on rv32Palmer Dabbelt2023-10-312-1/+3
| * | | | RISC-V: hwprobe: Expose Zicboz extension and its block sizeAndrew Jones2023-09-211-1/+1
| * | | | RISC-V: Enable cbo.zero in usermodeAndrew Jones2023-09-213-0/+18
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* | | | Merge tag 'mm-nonmm-stable-2023-11-02-14-08' of git://git.kernel.org/pub/scm/...Linus Torvalds2023-11-022-0/+13
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| * | | | riscv: kdump: use generic interface to simplify crashkernel reservationBaoquan He2023-10-042-0/+13
* | | | | Merge tag 'mm-stable-2023-11-01-14-33' of git://git.kernel.org/pub/scm/linux/...Linus Torvalds2023-11-021-0/+12
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| * | | | | mm: delete checks for xor_unlock_is_negative_byte()Matthew Wilcox (Oracle)2023-10-181-1/+0
| * | | | | riscv: implement xor_unlock_is_negative_byteMatthew Wilcox (Oracle)2023-10-181-0/+13
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* | | | | Merge tag 'kvm-riscv-6.7-1' of https://github.com/kvm-riscv/linux into HEADPaolo Bonzini2023-10-315-1/+51
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| * | | | | RISC-V: KVM: Forward SBI DBCN extension to user-spaceAnup Patel2023-10-201-0/+1
| * | | | | RISC-V: KVM: Allow some SBI extensions to be disabled by defaultAnup Patel2023-10-201-0/+4
| * | | | | RISC-V: KVM: Change the SBI specification version to v2.0Anup Patel2023-10-201-1/+1
| * | | | | RISC-V: Add defines for SBI debug console extensionAnup Patel2023-10-201-0/+7
| * | | | | RISCV: KVM: Add sstateen0 context save/restoreMayuresh Chitale2023-10-122-0/+9
| * | | | | RISCV: KVM: Add senvcfg context save/restoreMayuresh Chitale2023-10-122-0/+3
| * | | | | RISC-V: KVM: Enable Smstateen accessesMayuresh Chitale2023-10-122-0/+17
| * | | | | RISC-V: KVM: Add kvm_vcpu_configMayuresh Chitale2023-10-121-0/+7
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