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* Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-05-061-0/+6
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| * RISC-V: Add crash kernel supportNick Kossifidis2021-04-261-0/+1
| * RISC-V: Add kdump supportNick Kossifidis2021-04-261-1/+1
| * RISC-V: Add kexec supportNick Kossifidis2021-04-261-0/+5
* | riscv: syscall_table: Reduce W=1 compilation warnings noiseNanyong Sun2021-03-091-0/+1
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* riscv: Add kprobes supportedGuo Ren2021-01-141-0/+1
* riscv: Fixup patch_text panic in ftraceGuo Ren2021-01-141-0/+1
* riscv: Fixup wrong ftrace remove cflagGuo Ren2021-01-141-2/+2
* riscv: kernel: Drop unused clean ruleKefeng Wang2020-12-101-2/+0
* RISC-V: Add EFI runtime servicesAtish Patra2020-10-021-0/+2
* RISC-V: Remove CLINT related code from timer and archAnup Patel2020-08-201-1/+1
* riscv: Add jump-label implementationEmil Renner Berthing2020-07-301-0/+2
* riscv: Add KGDB supportVincent Chen2020-05-181-0/+1
* riscv: perf: RISCV_BASE_PMU should be independentKefeng Wang2020-05-121-1/+1
* riscv: Add SOC early init supportDamien Le Moal2020-04-031-0/+1
* riscv: Unaligned load/store handling for M_MODEDamien Le Moal2020-04-031-1/+1
* RISC-V: Support cpu hotplugAtish Patra2020-03-311-0/+1
* RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-311-0/+3
* RISC-V: Add cpu_ops and modify default booting methodAtish Patra2020-03-311-0/+2
* riscv: introduce interfaces to patch kernel codeZong Li2020-03-261-1/+3
* riscv: add nommu supportChristoph Hellwig2019-11-171-2/+1
* riscv: provide native clint access for M-modeChristoph Hellwig2019-11-171-0/+1
* riscv: cleanup the default power off implementationChristoph Hellwig2019-11-131-0/+1
* riscv: Add support for perf registers samplingMao Han2019-09-051-0/+1
* riscv: Add perf callchain supportMao Han2019-09-041-1/+2
* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
* RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel2019-03-261-3/+0
* Allow to disable FPU supportAlan Kao2018-10-221-1/+1
* Extract FPU context operations from entry.SAlan Kao2018-10-221-0/+1
* perf: riscv: preliminary RISC-V supportAlan Kao2018-06-041-0/+2
* RISC-V: Fixes to module loadingPalmer Dabbelt2018-04-021-0/+1
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| * RISC-V: Add sections of PLT and GOT for kernel moduleZong Li2018-04-021-0/+1
* | riscv/ftrace: Add dynamic function tracer supportAlan Kao2018-04-021-2/+3
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* riscv/ftrace: Add basic supportAlan Kao2018-01-301-0/+7
* RISC-V: Build InfrastructurePalmer Dabbelt2017-09-261-0/+33
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