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path: root/arch/riscv/kernel/cpu.c
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* RISC-V: fix ordering of Zbb extensionHeiko Stuebner2023-02-211-1/+1
* RISC-V: add zbb support to string functionsHeiko Stuebner2023-01-311-0/+1
* Merge patch series "Putting some basic order on isa extension lists"Palmer Dabbelt2023-01-191-15/+38
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| * RISC-V: resort all extensions in consistent ordersConor Dooley2023-01-171-2/+2
| * RISC-V: clarify ISA string ordering rules in cpu.cConor Dooley2023-01-171-13/+36
* | Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2022-12-141-3/+27
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| * | RISC-V: Cache SBI vendor valuesHeiko Stuebner2022-10-271-3/+27
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* / RISC-V: Fix /proc/cpuinfo cpumask warningAndrew Jones2022-10-271-0/+3
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* Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2022-10-141-0/+51
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| * RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputPalmer Dabbelt2022-10-131-0/+51
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| | * RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputAnup Patel2022-10-031-0/+51
* | | Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2022-10-111-0/+1
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| * | RISC-V: Probe Svinval extension form ISA stringMayuresh Chitale2022-10-021-0/+1
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* / RISC-V: Print SSTC in canonical orderPalmer Dabbelt2022-10-061-1/+1
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* RISC-V: Add Sstc extension supportPalmer Dabbelt2022-08-111-0/+1
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| * RISC-V: Enable sstc extension parsing from DTAtish Patra2022-08-111-0/+1
* | arch/riscv: add Zihintpause supportDao Lu2022-08-111-0/+1
* | riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt2022-08-101-0/+1
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| * | riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner2022-07-281-0/+1
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* / riscv: cpu: Add 64bit hartid support on RV64Sunil V L2022-07-191-11/+15
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* riscv: Don't output a bogus mmu-type on a no MMU kernelNiklas Cassel2022-05-211-0/+4
* riscv: add RISC-V Svpbmt extension supportHeiko Stuebner2022-05-111-0/+1
* riscv: cpu.c: don't use kernel-doc markers for commentsRandy Dunlap2022-03-311-2/+2
* RISC-V: Fix a comment typo in riscv_of_parent_hartid()Atish Patra2022-03-301-1/+1
* perf: RISC-V: Add support for SBI PMU and SscofpmfPalmer Dabbelt2022-03-211-0/+1
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| * RISC-V: Add sscofpmf extension supportAtish Patra2022-03-211-0/+1
* | RISC-V: Provide a fraemework for RISC-V ISA extensionsPalmer Dabbelt2022-03-171-2/+63
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| * RISC-V: Improve /proc/cpuinfo output for ISA extensionsAtish Patra2022-03-171-2/+63
* | riscv: mm: Set sv57 on defaultlyQinglin Pan2022-02-141-1/+3
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* riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfoAlexandre Ghiti2022-01-191-11/+12
* riscv: Use of_get_cpu_hwid()Rob Herring2021-10-201-1/+2
* RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel2020-06-091-0/+16
* RISC-V: Remove unsupported isa string info printAtish Patra2019-10-281-42/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra2019-04-301-2/+1
* RISC-V: Remove NR_CPUs check during hartid search from DTAtish Patra2019-03-041-4/+0
* riscv: treat cpu devicetree nodes without status as enabledJohan Hovold2019-02-111-7/+3
* riscv: fix riscv_of_processor_hartid() commentJohan Hovold2019-02-111-9/+9
* riscv: add missing newlines to printk messagesJohan Hovold2019-02-111-1/+1
* RISC-V: Fix of_node_* refcountAtish Patra2018-12-211-0/+1
* RISC-V: recognize S/U mode bits in print_isaPatrick Stählin2018-11-201-3/+6
* RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel2018-10-221-4/+6
* RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-3/+5
* RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-221-2/+5
* RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt2018-10-221-7/+61
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+108
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