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path: root/arch/riscv/kernel/cpufeature.c
Commit message (Expand)AuthorAgeFilesLines
* riscv: cpufeature: Fix extension subset checkingCharlie Jenkins2024-05-221-1/+1
* riscv: cpufeature: Fix thead vector hwcap removalCharlie Jenkins2024-05-221-2/+6
* Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2024-03-221-255/+1
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| * Merge patch series "riscv: Use Kconfig to set unaligned access speed"Palmer Dabbelt2024-03-131-255/+0
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| | * riscv: Set unaligned access speed at compile timeCharlie Jenkins2024-03-131-272/+0
| | * riscv: Decouple emulated unaligned accesses from access speedCharlie Jenkins2024-03-131-4/+21
| | * riscv: lib: Introduce has_fast_unaligned_access()Charlie Jenkins2024-03-131-3/+3
| * | perf: RISC-V: Introduce Andes PMU to support perf event samplingYu Chien Peter Lin2024-03-121-0/+1
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* | Merge patch series "riscv: cbo.zero fixes"Palmer Dabbelt2024-02-291-3/+13
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| * | riscv: Add a custom ISA extension for the [ms]envcfg CSRSamuel Holland2024-02-291-2/+12
| * | riscv: Fix enabling cbo.zero when running in M-modeSamuel Holland2024-02-291-1/+1
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* / RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUsConor Dooley2024-02-231-0/+15
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* Merge patch series "riscv: Add fine-tuned checksum functions"Palmer Dabbelt2024-01-171-3/+87
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| * riscv: Add static key for misaligned accessesCharlie Jenkins2024-01-171-3/+87
* | Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt2024-01-091-0/+2
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| * | riscv: add ISA extension parsing for ZacasClément Léger2024-01-091-0/+1
| * | riscv: add ISA extension parsing for ZtsoClément Léger2024-01-091-0/+1
* | | RISC-V: Remove the removed single-letter extensionsPalmer Dabbelt2024-01-031-4/+0
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* | riscv: add ISA extension parsing for ZfaClément Léger2023-12-121-0/+1
* | riscv: add ISA extension parsing for Zvfh[min]Clément Léger2023-12-121-0/+2
* | riscv: add ISA extension parsing for ZihintntlClément Léger2023-12-121-0/+1
* | riscv: add ISA extension parsing for Zfh/Zfh[min]Clément Léger2023-12-121-0/+2
* | riscv: add ISA extension parsing for vector cryptoClément Léger2023-12-121-0/+64
* | riscv: add ISA extension parsing for scalar cryptoEvan Green2023-12-121-23/+95
* | riscv: add ISA extension parsing for ZbcClément Léger2023-12-121-0/+1
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* Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-101-13/+79
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| * RISC-V: Probe misaligned access speed in parallelEvan Green2023-11-071-19/+77
| * riscv: don't probe unaligned access speed if already doneJisheng Zhang2023-11-051-0/+4
| * Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-051-1/+5
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| | * riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-011-0/+4
| | * riscv: annotate check_unaligned_access_boot_cpu() with __initClément Léger2023-11-011-1/+1
* | | Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-081-5/+12
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| * | RISC-V: clarify the QEMU workaround in ISA parserTsukasa OI2023-10-311-3/+4
| * | RISC-V: Enable cbo.zero in usermodeAndrew Jones2023-09-211-0/+6
| * | RISC-V: Make zicbom/zicboz errors consistentAndrew Jones2023-09-211-2/+2
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* | RISC-V: Detect Zicond from ISA stringAnup Patel2023-10-121-0/+1
* | RISC-V: Detect Smstateen extensionMayuresh Chitale2023-10-121-0/+1
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* Merge patch series "RISC-V: Probe for misaligned access speed"Palmer Dabbelt2023-09-081-0/+104
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| * RISC-V: Probe for unaligned access speedEvan Green2023-09-011-0/+104
* | Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-09-011-181/+340
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| * | RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa"Conor Dooley2023-07-251-1/+13
| * | RISC-V: enable extension detection from dedicated propertiesConor Dooley2023-07-251-4/+74
| * | RISC-V: split riscv_fill_hwcap() in 3Conor Dooley2023-07-251-168/+177
| * | RISC-V: add single letter extensions to riscv_isa_extConor Dooley2023-07-251-0/+13
| * | RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()Conor Dooley2023-07-251-21/+9
| * | RISC-V: shunt isa_ext_arr to cpufeature.cConor Dooley2023-07-251-0/+67
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* | Merge tag 'devicetree-header-cleanups-for-6.6' of git://git.kernel.org/pub/sc...Linus Torvalds2023-08-301-1/+0
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| * | riscv: Explicitly include correct DT includesRob Herring2023-08-281-1/+0
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* / RISC-V: Don't include Zicsr or Zifencei in I from ACPIPalmer Dabbelt2023-07-121-7/+2
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* Merge patch series "ISA string parser cleanups"Palmer Dabbelt2023-06-231-23/+85
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