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* Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-05-061-2/+4
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| * riscv: sifive: Apply errata "cip-453" patchVincent Chen2021-04-261-2/+4
* | riscv: keep interrupts disabled for BREAKPOINT exceptionJisheng Zhang2021-04-151-0/+3
* | riscv,entry: fix misaligned base for excp_vect_tableZihao Yu2021-04-011-0/+1
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* riscv: Trace irq on only interrupt is enabledAtish Patra2021-01-121-3/+3
* riscv: Enable interrupts during syscalls with M-ModeDamien Le Moal2021-01-071-0/+9
* riscv: return -ENOSYS for syscall -1Andreas Schwab2021-01-071-8/+1
* riscv: Cleanup unnecessary define in asm-offset.cGuo Ren2020-07-301-5/+1
* riscv: Enable context trackingGreentime Hu2020-07-301-1/+15
* riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORTGuo Ren2020-07-301-1/+33
* RISC-V: Remove do_IRQ() functionAnup Patel2020-06-091-1/+3
* Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-04-091-82/+61
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| * RISC-V: Inline the assembly register save/restore macrosPalmer Dabbelt2020-03-031-82/+61
* | riscv: fix seccomp reject syscall code pathTycho Andersen2020-03-051-8/+3
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* Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2020-01-281-2/+2
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| * sched/rt, riscv: Use CONFIG_PREEMPTIONThomas Gleixner2019-12-081-2/+2
* | riscv: reject invalid syscalls below -1David Abdurachmanov2019-12-271-0/+1
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* Merge branch 'next/nommu' into for-nextPaul Walmsley2019-11-221-31/+54
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| * riscv: add nommu supportChristoph Hellwig2019-11-171-0/+11
| * riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-31/+43
* | riscv: add support for SECCOMP and SECCOMP_FILTERDavid Abdurachmanov2019-10-291-2/+25
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* RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider2019-10-091-2/+1
* RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt2019-10-011-1/+20
* riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen2019-09-201-1/+5
* riscv: Using CSR numbers to access CSRsBin Meng2019-08-301-3/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-161-11/+11
* RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=yVincent Chen2019-01-231-1/+17
* riscv: add audit supportDavid Abdurachmanov2019-01-071-2/+2
* RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-221-1/+0
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| * RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2018-10-221-1/+0
* | Extract FPU context operations from entry.SAlan Kao2018-10-221-87/+0
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* RISC-V: implement low-level interrupt handlingChristoph Hellwig2018-08-131-2/+2
* RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handlerPalmer Dabbelt2018-03-141-4/+3
* RISC-V: Enable IRQ during exception handlingzongbox@gmail.com2018-02-201-2/+3
* riscv: disable SUM in the exception handlerChristoph Hellwig2018-01-301-3/+6
* riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-071-4/+4
* RISC-V: Task implementationPalmer Dabbelt2017-09-261-0/+464
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