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* Merge tag 'riscv-for-linus-5.11-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2020-12-181-1/+0
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| * riscv: Enable ARCH_STACKWALKKefeng Wang2020-11-251-1/+0
* | riscv: Set text_offset correctly for M-ModeSean Anderson2020-11-051-0/+5
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* RISC-V: Add PE/COFF header for EFI stubAtish Patra2020-10-021-0/+16
* RISC-V: Move DT mapping outof fixmapAnup Patel2020-10-021-1/+0
* RISC-V: Fix duplicate included thread_info.hTian Tao2020-09-151-1/+0
* riscv: Setup exception vector for nommu platformQiu Wenbo2020-08-141-8/+17
* RISC-V: Setup exception vector earlyAtish Patra2020-07-301-2/+8
* RISC-V: Skip setting up PMPs on trapsPalmer Dabbelt2020-05-181-1/+10
* riscv: Add SOC early init supportDamien Le Moal2020-04-031-0/+1
* RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-311-0/+26
* RISC-V: Move relocate and few other functions out of __initAtish Patra2020-03-311-71/+82
* riscv: set pmp configuration if kernel is running in M-modeGreentime Hu2020-02-181-0/+6
* riscv: Add KASAN supportNick Hu2020-01-221-0/+3
* riscv: make sure the cores stay looping in .Lsecondary_parkGreentime Hu2020-01-151-6/+10
* riscv: Fixup obvious bug for fp-regs resetGuo Ren2020-01-121-1/+1
* riscv: fix scratch register clearing in M-mode.Greentime Hu2019-12-201-1/+1
* riscv: add nommu supportChristoph Hellwig2019-11-171-0/+6
* riscv: clear the instruction cache and all registers when bootingChristoph Hellwig2019-11-171-1/+87
* riscv: read the hart ID from mhartid on bootDamien Le Moal2019-11-171-0/+8
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-6/+6
* arch/riscv: disable excess harts before picking main boot hartXiang Wang2019-09-201-3/+5
* Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2019-09-161-1/+1
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| * riscv: Using CSR numbers to access CSRsBin Meng2019-08-301-1/+1
* | riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley2019-09-131-2/+2
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* RISC-V: Add an Image header that boot loader can parse.Atish Patra2019-07-111-0/+32
* RISC-V: Setup initial page tables in two stagesAnup Patel2019-07-091-8/+9
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Avoid using invalid intermediate translationsPalmer Dabbelt2019-05-161-2/+10
* RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-161-8/+8
* riscv: cleanup the parse_dtb calling conventionsChristoph Hellwig2019-04-251-2/+1
* riscv: simplify the stack pointer setup in head.SChristoph Hellwig2019-04-251-4/+1
* riscv: clear all pending interrupts when bootingChristoph Hellwig2019-04-251-1/+2
* RISC-V: Build flat and compressed kernel imagesAnup Patel2018-11-201-0/+10
* RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-1/+3
* RISC-V: Add the directive for alignment of stvec's valueZong Li2018-08-131-0/+2
* Rename sbi_save to parse_dtb to improve code readabilityMichael Clark2018-02-201-1/+1
* riscv: rename sptbr to satpChristoph Hellwig2018-01-301-3/+3
* RISC-V: move empty_zero_page definition to C and export itOlof Johansson2017-11-301-3/+0
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+157
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