summaryrefslogtreecommitdiffstats
path: root/arch/riscv/kernel/head.S
Commit message (Expand)AuthorAgeFilesLines
* riscv: fix -Wundef warning for CONFIG_RISCV_BOOT_SPINWAITMasahiro Yamada2023-01-191-1/+1
* riscv: Initialize thread pointer before calling C functionsAlexandre Ghiti2022-06-011-0/+1
* RISC-V: Split out the XIP fixups into their own filePalmer Dabbelt2022-05-251-0/+1
* RISC-V: Add arch functions for non-retentive suspend entry/exitAnup Patel2022-03-101-21/+0
* RISC-V: Rename relocate() and make it globalAnup Patel2022-03-101-3/+4
* RISC-V: Move spinwait booting method to its own configAtish Patra2022-01-201-4/+4
* RISC-V: Move the entire hart selection via lottery to SMPAtish Patra2022-01-201-2/+6
* RISC-V: Use __cpu_up_stack/task_pointer only for spinwait methodAtish Patra2022-01-201-2/+2
* RISC-V: Avoid using per cpu array for ordered bootingAtish Patra2022-01-201-9/+10
* RISC-V: Introduce sv48 support without relocatable kernelPalmer Dabbelt2022-01-191-1/+2
|\
| * riscv: Implement sv48 supportAlexandre Ghiti2022-01-191-1/+2
* | riscv: head: remove useless __PAGE_ALIGNED_BSS and .balignJisheng Zhang2022-01-091-4/+0
* | riscv: head: make secondary_start_common() staticJisheng Zhang2022-01-091-3/+2
* | riscv/head: fix misspelling of guaranteedhasheddan2022-01-071-1/+1
|/
* Merge tag 'riscv-for-linus-5.16-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-11-131-0/+12
|\
| * riscv: remove .text section size limitation for XIPVitaly Wool2021-10-261-0/+12
* | Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linu...Linus Torvalds2021-11-011-1/+0
|\ \
| * | riscv: rely on core code to keep thread_info::cpu updatedArd Biesheuvel2021-09-301-1/+0
| |/
* / riscv: fix misalgned trap vector base addressChen Lu2021-10-271-0/+1
|/
* riscv: Introduce structure that group all variables regarding kernel mappingAlexandre Ghiti2021-07-051-2/+2
* RISC-V: enable XIPVitaly Wool2021-04-261-1/+45
* riscv: Move kernel mapping outside of linear mappingAlexandre Ghiti2021-04-261-1/+2
* riscv: add BUILTIN_DTB support for MMU-enabled targetsVitaly Wool2021-02-181-0/+4
* Merge tag 'riscv-for-linus-5.11-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2020-12-181-1/+0
|\
| * riscv: Enable ARCH_STACKWALKKefeng Wang2020-11-251-1/+0
* | riscv: Set text_offset correctly for M-ModeSean Anderson2020-11-051-0/+5
|/
* RISC-V: Add PE/COFF header for EFI stubAtish Patra2020-10-021-0/+16
* RISC-V: Move DT mapping outof fixmapAnup Patel2020-10-021-1/+0
* RISC-V: Fix duplicate included thread_info.hTian Tao2020-09-151-1/+0
* riscv: Setup exception vector for nommu platformQiu Wenbo2020-08-141-8/+17
* RISC-V: Setup exception vector earlyAtish Patra2020-07-301-2/+8
* RISC-V: Skip setting up PMPs on trapsPalmer Dabbelt2020-05-181-1/+10
* riscv: Add SOC early init supportDamien Le Moal2020-04-031-0/+1
* RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-311-0/+26
* RISC-V: Move relocate and few other functions out of __initAtish Patra2020-03-311-71/+82
* riscv: set pmp configuration if kernel is running in M-modeGreentime Hu2020-02-181-0/+6
* riscv: Add KASAN supportNick Hu2020-01-221-0/+3
* riscv: make sure the cores stay looping in .Lsecondary_parkGreentime Hu2020-01-151-6/+10
* riscv: Fixup obvious bug for fp-regs resetGuo Ren2020-01-121-1/+1
* riscv: fix scratch register clearing in M-mode.Greentime Hu2019-12-201-1/+1
* riscv: add nommu supportChristoph Hellwig2019-11-171-0/+6
* riscv: clear the instruction cache and all registers when bootingChristoph Hellwig2019-11-171-1/+87
* riscv: read the hart ID from mhartid on bootDamien Le Moal2019-11-171-0/+8
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-6/+6
* arch/riscv: disable excess harts before picking main boot hartXiang Wang2019-09-201-3/+5
* Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2019-09-161-1/+1
|\
| * riscv: Using CSR numbers to access CSRsBin Meng2019-08-301-1/+1
* | riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley2019-09-131-2/+2
|/
* RISC-V: Add an Image header that boot loader can parse.Atish Patra2019-07-111-0/+32
* RISC-V: Setup initial page tables in two stagesAnup Patel2019-07-091-8/+9
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 20:24:48 +0000