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path: root/arch/riscv/kernel/smpboot.c
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* RISC-V: Remove CLINT related code from timer and archAnup Patel2020-08-201-1/+0
* RISC-V: Add mechanism to provide custom IPI operationsAnup Patel2020-08-201-2/+1
* RISC-V: Fix build warning for smpboot.cAtish Patra2020-08-041-1/+1
* RISC-V: Setup exception vector earlyAtish Patra2020-07-301-1/+1
* riscv: Fixup lockdep_assert_held with wrong param cpu_runningZong Li2020-07-301-1/+0
* RISC-V: Use a local variable instead of smp_processor_id()Greentime Hu2020-06-291-3/+4
* RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-311-1/+1
* RISC-V: Add cpu_ops and modify default booting methodAtish Patra2020-03-311-21/+30
* riscv: provide native clint access for M-modeChristoph Hellwig2019-11-171-0/+4
* riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley2019-10-281-1/+1
* riscv: add missing header file includesPaul Walmsley2019-10-281-0/+1
* riscv: add prototypes for assembly language functions from head.SPaul Walmsley2019-10-281-0/+2
* RISC-V: Parse cpu topology during boot.Atish Patra2019-07-221-0/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-301-9/+1
* RISC-V: Support nr_cpus command line option.Atish Patra2019-05-161-1/+9
* RISC-V: Implement nosmp commandline option.Atish Patra2019-04-301-1/+11
* RISC-V: Compare cpuid with NR_CPUS before mapping.Atish Patra2019-03-041-0/+5
* RISC-V: Do not wait indefinitely in __cpu_upAtish Patra2019-03-041-3/+12
* riscv: use for_each_of_cpu_node iteratorJohan Hovold2019-02-111-2/+2
* RISC-V: fix bad use of of_node_putAndreas Schwab2019-01-231-5/+1
* RISC-V: Fix of_node_* refcountAtish Patra2018-12-211-1/+5
* RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-9/+16
* RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra2018-10-221-2/+3
* RISC-V: Use mmgrab()Palmer Dabbelt2018-10-221-1/+2
* RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt2018-10-221-4/+5
* RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-221-1/+1
* RISC-V: Disable preemption before enabling interruptsAtish Patra2018-10-221-1/+5
* RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt2018-10-221-0/+4
* clocksource: new RISC-V SBI timer driverPalmer Dabbelt2018-08-131-1/+0
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+114
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