summaryrefslogtreecommitdiffstats
path: root/arch/riscv/kernel
Commit message (Expand)AuthorAgeFilesLines
* Fix a handful of audit-related issuePalmer Dabbelt2019-01-072-3/+10
|\
| * riscv: fix trace_sys_exit hookDavid Abdurachmanov2019-01-071-1/+1
| * riscv: define CREATE_TRACE_POINTS in ptrace.cDavid Abdurachmanov2019-01-071-0/+2
| * riscv: audit: add audit hook in do_syscall_trace_enter/exit()David Abdurachmanov2019-01-071-0/+5
| * riscv: add audit supportDavid Abdurachmanov2019-01-071-2/+2
* | RISC-V: Support MODULE_SECTIONS mechanism on RV32Zong Li2019-01-071-14/+16
* | riscv: don't stop itself in smp_send_stopAndreas Schwab2019-01-071-7/+36
* | arch: riscv: support kernel command line forcing when no DTB passedPaul Walmsley2019-01-071-1/+8
* | RISC-V: Make BSS section as the last section in vmlinux.lds.SAnup Patel2019-01-071-2/+6
* | Remove 'type' argument from access_ok() functionLinus Torvalds2019-01-031-2/+2
* | RISC-V: Move from EARLY_PRINTK to SBI earlyconPalmer Dabbelt2018-12-211-28/+0
|\ \
| * | RISC-V: Remove EARLY_PRINTK supportAnup Patel2018-12-171-28/+0
| |/
* | riscv: remove unused variable in ftraceDavid Abdurachmanov2018-12-211-1/+0
* | RISC-V: add of_node_put()Yangtao Li2018-12-211-0/+1
* | RISC-V: Fix of_node_* refcountAtish Patra2018-12-215-1/+20
|/
* Merge tag 'trace-v4.20-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/...Linus Torvalds2018-11-301-12/+2
|\
| * riscv/function_graph: Simplify with function_graph_enter()Steven Rostedt (VMware)2018-11-271-12/+2
* | RISC-V: recognize S/U mode bits in print_isaPatrick Stählin2018-11-201-3/+6
* | RISC-V: Build flat and compressed kernel imagesAnup Patel2018-11-202-1/+11
|/
* RISC-V: Silence some module warnings on 32-bitOlof Johansson2018-11-121-6/+6
* RISC-V: properly determine hardware capsAndreas Schwab2018-10-311-3/+5
* RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-227-47/+195
|\
| * RISC-V: Show IPI statsAnup Patel2018-10-222-7/+40
| * RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel2018-10-221-4/+6
| * RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-225-22/+45
| * RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-222-0/+23
| * RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra2018-10-221-2/+3
| * RISC-V: Use mmgrab()Palmer Dabbelt2018-10-221-1/+2
| * RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt2018-10-221-4/+5
| * RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-222-3/+6
| * RISC-V: Disable preemption before enabling interruptsAtish Patra2018-10-221-1/+5
| * RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt2018-10-221-0/+4
| * RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt2018-10-221-7/+61
| * RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt2018-10-221-7/+0
| * RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2018-10-222-3/+2
* | RISC-V: Fix some RV32 bugs and build failuresPalmer Dabbelt2018-10-221-0/+3
|\ \
| * | RISC-V: Use swiotlb on RV64 onlyZong Li2018-10-221-0/+3
| |/
* | riscv: Add support to no-FPU systemsPalmer Dabbelt2018-10-226-115/+168
|\ \
| * | Auto-detect whether a FPU existsAlan Kao2018-10-223-3/+15
| * | Allow to disable FPU supportAlan Kao2018-10-223-2/+9
| * | Refactor FPU code in signal setup/return proceduresAlan Kao2018-10-221-27/+41
| * | Extract FPU context operations from entry.SAlan Kao2018-10-223-87/+107
| |/
* | RISC-V: remove the unused return_to_handler exportChristoph Hellwig2018-10-221-1/+0
* | RISC-V: Add FP register ptrace support for gdb.Jim Wilson2018-10-221-0/+52
* | RISC-V: Mask out the F extension on systems without DPalmer Dabbelt2018-10-221-0/+7
* | RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt2018-10-221-7/+0
|/
* RISCV: Fix end PFN for low memoryAtish Patra2018-10-021-1/+1
* riscv: Do not overwrite initrd_start and initrd_endGuenter Roeck2018-09-041-7/+0
* RISC-V: Use a less ugly workaround for unused variable warningsPalmer Dabbelt2018-08-281-14/+1
* RISC-V: Define sys_riscv_flush_icache when SMP=nPalmer Dabbelt2018-08-201-2/+10
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-24 14:40:44 +0000