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* RISC-V: gp_in_global needs register keywordPalmer Dabbelt2020-05-211-1/+1
* riscv: stacktrace: Fix undefined reference to `walk_stackframe'Kefeng Wang2020-05-121-1/+1
* riscv: perf: RISCV_BASE_PMU should be independentKefeng Wang2020-05-121-1/+1
* riscv: perf_event: Make some funciton staticKefeng Wang2020-05-111-4/+4
* riscv: force __cpu_up_ variables to put in data sectionZong Li2020-05-041-2/+2
* riscv: add Linux note to vdsoAndreas Schwab2020-05-042-1/+13
* RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel2020-05-041-3/+80
* RISC-V: Export riscv_cpuid_to_hartid_mask() APIAnup Patel2020-05-041-0/+2
* riscv: sbi: Fix undefined reference to sbi_shutdownKefeng Wang2020-04-211-5/+8
* riscv: sbi: Correct sbi_shutdown() and sbi_clear_ipi() exportKefeng Wang2020-04-211-2/+2
* riscv: fix vdso build with lldIlie Halip2020-04-211-3/+3
* RISC-V: stacktrace: Declare sp_in_global outside ifdefGuenter Roeck2020-04-211-2/+2
* Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-04-0918-206/+1679
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| * riscv: Add SOC early init supportDamien Le Moal2020-04-034-0/+36
| * riscv: Unaligned load/store handling for M_MODEDamien Le Moal2020-04-033-4/+395
| * RISC-V: Support cpu hotplugAtish Patra2020-03-314-1/+140
| * RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-316-3/+121
| * RISC-V: Export SBI error to linux error mapping functionAtish Patra2020-03-311-1/+2
| * RISC-V: Add cpu_ops and modify default booting methodAtish Patra2020-03-314-21/+113
| * RISC-V: Move relocate and few other functions out of __initAtish Patra2020-03-312-72/+86
| * RISC-V: Implement new SBI v0.2 extensionsAtish Patra2020-03-311-4/+249
| * RISC-V: Introduce a new config for SBI v0.1Atish Patra2020-03-311-23/+109
| * RISC-V: Add basic support for SBI v0.2Atish Patra2020-03-312-2/+246
| * riscv: patch code by fixmap mappingZong Li2020-03-261-9/+4
| * riscv: introduce interfaces to patch kernel codeZong Li2020-03-262-1/+123
| * riscv: add macro to get instruction lengthZong Li2020-03-261-1/+2
| * riscv: add alignment for text, rodata and data sectionsZong Li2020-03-261-1/+4
| * riscv: move exception table immediately after RO_DATAZong Li2020-03-261-2/+4
| * RISC-V: Inline the assembly register save/restore macrosPalmer Dabbelt2020-03-031-82/+61
| * RISC-V: Stop relying on GCC's register allocator's hueristicsPalmer Dabbelt2020-03-032-5/+7
| * RISC-V: Stop putting .sbss in .sdataPalmer Dabbelt2020-03-031-1/+0
| * riscv: force hart_lottery to put in .sdata sectionZong Li2020-03-031-2/+6
* | Merge tag 'spdx-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gre...Linus Torvalds2020-04-032-0/+2
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| * | .gitignore: add SPDX License IdentifierMasahiro Yamada2020-03-252-0/+2
* | | Merge tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-03-301-1/+1
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| * | | irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra2020-03-161-1/+1
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* | | riscv: fix the IPI missing issue in nommu modeGreentime Hu2020-03-181-1/+1
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* | riscv: fix seccomp reject syscall code pathTycho Andersen2020-03-052-14/+8
* | riscv: avoid the PIC offset of static percpu data in module beyond 2G limitsVincent Chen2020-03-031-0/+16
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* RISC-V: Don't enable all interrupts in trap_init()Anup Patel2020-02-181-2/+2
* riscv: set pmp configuration if kernel is running in M-modeGreentime Hu2020-02-181-0/+6
* Merge tag 'riscv-for-linus-5.6-mw0' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2020-01-314-0/+11
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| * riscv: Add KASAN supportNick Hu2020-01-224-0/+11
* | Merge tag 'tty-5.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/greg...Linus Torvalds2020-01-291-4/+0
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| * | arch/riscv/setup: Drop dummy_con initializationArvind Sankar2020-01-141-4/+0
* | | Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2020-01-281-2/+2
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| * | Merge tag 'v5.5-rc3' into sched/core, to pick up fixesIngo Molnar2019-12-251-1/+1
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| * | | sched/rt, riscv: Use CONFIG_PREEMPTIONThomas Gleixner2019-12-081-2/+2
* | | | riscv: delete temporary filesIlie Halip2020-01-181-1/+2
* | | | riscv: make sure the cores stay looping in .Lsecondary_parkGreentime Hu2020-01-151-6/+10
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