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path: root/arch/riscv/mm/context.c
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* riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong2023-03-211-1/+1
* riscv: asid: Fixup stale TLB entry cause application crashGuo Ren2023-03-091-10/+20
* Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich2023-03-091-10/+0
* riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich2022-12-081-0/+10
* riscv: Implement sv48 supportAlexandre Ghiti2022-01-191-2/+2
* riscv: mm: don't advertise 1 num_asid for 0 asid bitsVineet Gupta2021-10-041-3/+5
* riscv: add ASID-based tlbflushing methodsGuo Ren2021-06-301-1/+1
* riscv: mm: Use better bitmap_zalloc()Kefeng Wang2021-06-081-2/+1
* riscv: Add __init section marker to some functions againJisheng Zhang2021-05-291-1/+1
* riscv: Optimize switch_mm by passing "cpu" to flush_icache_deferred()Jisheng Zhang2021-05-251-3/+4
* RISC-V: Implement ASID allocatorAnup Patel2021-02-181-4/+261
* riscv: add nommu supportChristoph Hellwig2019-11-171-0/+2
* riscv: add missing header file includesPaul Walmsley2019-10-281-0/+1
* riscv: Using CSR numbers to access CSRsBin Meng2019-08-301-6/+1
* riscv: move switch_mm to its own fileGary Guo2019-05-161-0/+69
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